A 0.18 μm CMOS single-inductor single-stage quadrature frontend for GNSS receiver

Abstract

This paper presents an improved merged architecture for a low-IF GNSS receiver frontend, where the bias current and functions are reused in a stacked quadrature LNA-mixer-VCO. Only a single spiral inductor is implemented for the LC resonator and an extra 1/2 frequency divider is added as the quadrature LO signal generator. The details of the design are presented. The gain plan and noise figure are discussed. The phase noise, quadrature accuracy and power consumption are improved. The test chip is fabricated though a 0.18 m RF CMOS process. The measured noise figure is 5.4 dB on average, with a gain of 43 dB and a IIP3 of -39 dBm. The measured phase noise is better than -105 dBc/Hz at 1 MHz offset. The total power consumption is 19.8 mW with a 1.8 V supply. The experimental results satisfy the requirements for GNSS applications.