A 0.4-mW, 4.7-ps Resolution Single-Loop TDC Using a Half-Delay Time Integrator

Abstract

A compact, low-power, single-loop third-order delta-sigma ( ) time-to-digital converter (TDC) for time-mode signal processing is presented in this brief. In general, a high-resolution TDC requires a cascadable time integrator to increase the order of the loop filter. However, implementing the time integrator has been very challenging owing to the difficulty in storing time information. In this brief, we present a low-power half-delay time integrator, which is simply composed of two AND gates, a charge pump, and a comparator. The proposed time integrator can be easily cascaded (serially connected) to implement a loop filter with high-order noise shaping. The prototype TDC fabricated in 0.11-μm CMOS process occupies an active area of 0.11 mm 2 , consuming 0.4 mW from a 1.2 V supply. It achieves the dynamic range of 81 dB over a signal bandwidth of 50 kHz, and the resolution of 4.7 ps over a measurable range of 39.06 ns, which is half the clock period.Index Terms-Delta-sigma ( ) modulator, high resolution, low power, time-to-digital converter (TDC). 1063-8210

64 × 64 GM-APD array-based readout integrated circuit for 3D imaging applications

“…The third array architecture is a trade-off between the previous two complementary structures [6,7], where only a low-segment TDC is located outside pixels and shared by all (or some) pixels. In contrast, the high-segment TDC is located in the interior of each pixel.…”

Design of a third-order delta-sigma TDC with error-feedback structure

“…The delta-sigma MASH modulators were investigated for various applications [4,5]. The delta-sigma TDC approaches were researched for increasing time resolution [6,7]. Ref.…”

“…Ref. [6] adopted a single loop delta-sigma (DS) TDC using a charge pump circuit as an integrator. It requires a large capacitor in the integrator and a ramp circuit for quantization.…”