A 0.7 μm-Pitch 108 Mpixel Nonacell-Based CMOS Image Sensor with Decision-Feedback Technique

Jun, Jae-Hoon; Seo, Haneol; Kwon, Hyukbin; Lee, Jongyeon; Yoon, Beomsoo; Lee, Youngwoo; Kim, Yongbin; Joo, Woong; Lee, Jesuk; Koh, Kyoungmin

doi:10.1109/iscas48785.2022.9937226

Cited by 7 publications

(10 citation statements)

References 10 publications

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Section: Introductionmentioning

confidence: 99%

“…Various types of sensing systems are used in the era of the Internet of Everything [ 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 ]. With the advent of the Fourth Industrial Revolution, the demand for image sensor-related products has been increasing rapidly [ 5 , 6 , 7 , 8 , 9 , 10 ]. This enormous demand is not limited to consumer products and is continually expanding into defense, security, privacy, autonomous driving, and space science.…”

Section: Introductionmentioning

confidence: 99%

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A Comprehensive Methodology for Optimizing Read-Out Timing and Reference DAC Offset in High Frame Rate Image Sensing Systems

Jun

2023

Sensors

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This paper presents a comprehensive timing optimization methodology for power-efficient high-resolution image sensors with column-parallel single-slope analog-to-digital converters (ADCs). The aim of the method is to optimize the read-out timing for each period in the image sensor’s operation, while considering various factors such as ADC decision time, slew rate, and settling time. By adjusting the ramp reference offset and optimizing the amplifier bandwidth of the comparator, the proposed methodology minimizes the power consumption of the amplifier array, which is one of the most power-hungry circuits in the system, while maintaining a small color linearity error and ensuring optimal performance. To demonstrate the effectiveness of the proposed method, a power-efficient 108 MP 3-D stacked CMOS image sensor with a 10-bit column-parallel single-slope ADC array was implemented and verified. The image sensor achieved a random noise of 1.4 e-rms, a column fixed-pattern noise of 66 ppm at an analog gain of 16, and a remarkable figure-of-merit (FoM) of 0.71 e-·nJ. The sensor utilized a one-row read-out time of 6.9 µs, an amplifier bandwidth of 1.1 MHz, and a reference digital-to-analog converter (DAC) offset of 512 LSB. This timing optimization methodology enhances energy efficiency in high-resolution image sensors, enabling higher frame rates and improved system performance. It could be adapted for various imaging applications requiring optimized performance and reduced power consumption, making it a valuable tool for designers aiming to achieve optimal performance in power-sensitive applications.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Comprehensive Methodology for Optimizing Read-Out Timing and Reference DAC Offset in High Frame Rate Image Sensing Systems

Jun

2023

Sensors

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“…With the help of correction techniques, this design achieves 10 FPS. The advanced 3D process CIS achieves the same frame rate [ 17 ], but this design has a much larger pixel size.…”

Section: Simulation Results and Analysis Of Delay Detection And Accur...mentioning

confidence: 99%

“…As a result, the signal settling time is long, limiting the readout speed of the image sensor. This makes the frame rate of the very-large-pixel-array image sensor only a few frames per second [ 7 , 16 , 17 ]. Using the TX signals on the left and right sides of the pixel array as an example, inconsistencies in the row driver output signals on both sides of the pixel array will affect the frame rate.…”

Section: Introductionmentioning

confidence: 99%

Synchronous Driving Method for Stitching Pixel Arrays Based on an Adaptive Correction Technique

Liu,

Guo,

Cheng

et al. 2024

Sensors

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With the application of stitching technology in large-pixel-array CMOS image sensors, the problem of non-synchronized output signals from pixel array bilateral driver circuits has become progressively more serious and has led to the DC perforation of bilateral driver circuits, while conventional clock tree synchronization design methodology does not apply to stitching technology. Therefore, this paper analyses reasons for the inconsistency in the output signals of bilateral driving circuits and proposes a synchronous driving method applicable to stitching pixel arrays based on the idea of on-chip output signal delay detection and calibration. This method detects and corrects the non-synchrony of the row driver output signals on both sides according to changes in the operating environment of the chip. This method is characterized by a simple structure and high reliability. Finally, based on the 55 nm stitching process, simulations are carried out in a CMOS image sensor with a chip area of 77 mm × 84 mm to verify that this method is feasible. This large image sensor with a 150 M pixel array has a frame rate of over 10 FPS.

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“…A decision-feedback technique was proposed to control the dynamic current path of the CS amplifier and remove the signal dependency of the power consumption of the comparator [17,18]. The proposed feedback logic aims to disable the current path of the second stage amplifier using the flag of the decision signal.…”

Section: Fig 2 Timing Diagram Of the Single-slope Adc With The Curren...mentioning

confidence: 99%

A 10‐bit 13.3 µW single‐slope analog‐to‐digital converter with auto‐zero power‐down technique

Lee,

Kim,

Jun

2024

Electronics Letters

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This letter presents a low‐power single‐slope analog‐to‐digital converter (ADC) for column‐parallel architectures. A simple and effective design technique is proposed to solve the input‐dependent power consumption problem of the conventional single‐slope ADCs. A decision‐feedback loop is implemented in the second stage of the comparator. Based on the negative‐feedback path, which is activated after the signal decision of the comparator, the input‐dependent dynamic current path in the amplifier is disabled. Furthermore, an additional low‐power design technique is proposed to save the power consumption of the ADC by optimizing the offset cancelling auto‐zero period. With the combination of the proposed techniques, the power consumption of the single‐slope ADC can be effectively saved while suppressing the dynamic current.

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A 0.7 μm-Pitch 108 Mpixel Nonacell-Based CMOS Image Sensor with Decision-Feedback Technique

Cited by 7 publications

References 10 publications

A Comprehensive Methodology for Optimizing Read-Out Timing and Reference DAC Offset in High Frame Rate Image Sensing Systems

A Comprehensive Methodology for Optimizing Read-Out Timing and Reference DAC Offset in High Frame Rate Image Sensing Systems

Synchronous Driving Method for Stitching Pixel Arrays Based on an Adaptive Correction Technique

A 10‐bit 13.3 µW single‐slope analog‐to‐digital converter with auto‐zero power‐down technique

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