A 1.08pJ/bit DisplayPort RX with Combined AFE Offset Cancellation and Training-Less Link Setup

Ge, Yufeng; Jiang, Zheng; Fu, Yibin; Zhang, Yaolong; Wang, Jingbo; Zhang, Hong

doi:10.1109/isocc62682.2024.10762342

2024 21st International SoC Design Conference (ISOCC) 2024

DOI: 10.1109/isocc62682.2024.10762342

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A 1.08pJ/bit DisplayPort RX with Combined AFE Offset Cancellation and Training-Less Link Setup

Yufeng Ge,

Zheng Jiang,

Yibin Fu

et al.

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A 1.08pJ/bit DisplayPort RX with Combined AFE Offset Cancellation and Training-Less Link Setup

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References 6 publications

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