A 1.2 V 8-bit 1 MS/s SAR ADC with Res–Cap segment DAC for temperature sensor in LTE

Wu, Haijun; Li, B.; Huang, Weichao; Li, Z. P.; Zou, Mei; Wang, Y. P.

doi:10.1007/s10470-012-9890-z

Cited by 4 publications

(7 citation statements)

References 13 publications

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“…A basic TIQ Comparator circuit consists of two cascaded CMOS inverters, as shown Figure 2 (YOO et al, 2003). The first inverter works as voltage reference to the ADC system.…”

Section: Methodsmentioning

confidence: 99%

“…The first inverter works as voltage reference to the ADC system. The second inverter works as the gain booster to keep linearity in balance from the voltage rising and falling intervals (YOO et al, 2003). In previous researches several methods for design of TIQ-comparator have been studied, such as: the analog input signal quantization level is set in the first stage by changing the voltage transfer curve (VTC) by transistor sizing (TANGEL; CHOY, 2004) and (SUDAKAR et al, 2011), the size of both transistor channel lengths, L and width, W are adjusted (YOO et al, 2003), third, by only adjusting W and L is fixed (TANGEL;CHOY, 2004).…”

Section: Methodsmentioning

confidence: 99%

“…The ADC which is in accordance with that purpose is a Flash-ADC by TIQ-Comparator application. The Flash-ADC has many advantages, such as high speed, high linearity, low voltage and reduced power dissipation (YOO et al, 2003). Previous researches have undertaken a variety of methods to get the best performance of ADC, as Table 1 shows.…”

Section: Introductionmentioning

confidence: 99%

“…Table 1 shows that previous research generally developed design flash ADC with the lowest power Acta Scientiarum. Technology Maringá, v. 37, n. 1, p. 33-40, Jan.-Mar., 2015 (WU et al, 2012) proposed the SAR ADC design method with a power dissipation of 1200 μW and (SAHOO; RAZAVI, 2009) proposed a method pipeline ADC with 348 mW power dissipation, but they did not get a lower power consumption compared to the flash ADC. Current research proposed a low power dissipation flash ADC design with TIQ-comparator, encoder and PISO register development to obtain the best performance which is compatible for use with the temperature sensor system.…”

Section: Introductionmentioning

confidence: 99%

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<b>Design of a low-power flash analog-to-digital converter chip for temperature sensors in 0.18 µm CMOS process

Reaz

Jalil

et al. 2015

Acta Sci. Technol.

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ABSTRACT. Current paper proposes a simple design of a 6-bit flash analog-to-digital converter (ADC) by process in 0.18 μm CMOS. ADC is expected to be used within a temperature sensor which provides analog data output having a range of 360 mV to 560 mV. The complete system consisting of three main blocks, which are the threshold inverter quantization (TIQ)-comparator, the encoder and the parallel input serial output (PISO) register. The TIQ-comparator functions as quantization of the analog data to the thermometer code. The encoder converts this thermometer code to 6-bit binary code and the PISO register transforms the parallel data into a data series. The design aims to get a flash ADC on low power dissipation, small size and compatible with the temperature sensors. The method is proposed to set each of the transistor channel length to find out the threshold voltage difference of the inverter on the TIQ comparator. A portion design encoder and PISO registers circuit selected a simple circuit with the best performance from previous studies and adjusted to this system. The design has an input range of 285 to 600 mV and 6-bit resolution output. The chip area of the designed ADC is 844.48 x 764.77 μm 2 and the power dissipation is 0.162 μW with 1.6 V supply voltage.Keywords: flash ADC, temperature sensors, serial output.Projeto de um conversor analógico-digital flash de baixa potência para sensores de temperatura em processo CMOS a 0,18 μm RESUMO: Este trabalho propõe um projeto simples de um conversor analógico-digital (ADC) flash de 6-bits por processo de CMOS a 0,18 μm. Este dispositivo está previsto para ser usado dentro de um sensor de temperatura, o que proporciona uma saída analógica de dados dentro de intervalo de 360 mV a 560 mV. O sistema completo consiste em três blocos principais, que são o comparador de tipo (TIQ)-quantização de inversor de limiar, o codificador e o registrador de saída serial, a parte de entrada em paralelo (PISO). O comparador (TIQ) funciona como quantização dos dados analógicos para termômetro. O codificador converte este código de termômetro para código binário de 6-bits e o registrador PISO transforma os dados paralelos em uma série de dados. O objetivo do projeto é obter um ADC flash com baixa dissipação de potência, tamanho pequeno e compatível com os sensores de temperatura. O método é proposto para definir o comprimento de cada canal de transistor, para encontrar a diferença de tensão de limiar do inversor em cada comparador TIQ. Foram selecionadas partes de um codificador circuito registrador PISO em um circuito simples, e apresentaram melhor desempenho em relação aos estudos anteriores e foram ajustados a este sistema. O projeto tem um intervalo de entrada de 285-600 mV e saída de resolução de 6-bits. A área do chip do ADC projetado é 844,48 x 764,77 μm 2 e a dissipação de energia é 0,162 μW, com tensão de alimentação de 1,6 V.Palavras-chave: ADC flash, sensores de temperatura, saída serial.

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“…A basic TIQ Comparator circuit consists of two cascaded CMOS inverters, as shown Figure 2 (YOO et al, 2003). The first inverter works as voltage reference to the ADC system.…”

Section: Methodsmentioning

confidence: 99%

Section: Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

<b>Design of a low-power flash analog-to-digital converter chip for temperature sensors in 0.18 µm CMOS process

Reaz

Jalil

et al. 2015

Acta Sci. Technol.

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show abstract

“…An inverter based design of ADC proposed by [5], shows the lowest power dissipation of only 1,66 μW. Besides, [6] proposed SAR ADC design method with a power dissipation of 1200 μW and [7] proposed a pipelined ADC with 348 mW power dissipation. But they did not get a lower power consumption compared to Flash ADC.…”

Section: Introductionmentioning

confidence: 99%

A low power serial output flash ADC in 0,18 µm CMOS process

Reaz

Amin

et al. 2015

Teh. vjesn.

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Original scientific paper This paper proposes a simple design of a flash analog-to-digital converter (ADC) in 0,18 μm CMOS technology. This ADC is expected to be used within a temperature sensor, which provides analog data output having a range of 360 mV to 560 mV. This system consists of three main blocks: the threshold inverter quantization (TIQ)-comparator, encoder and parallel input serial output (PISO) register. The design goal is to get a flash ADC with low power dissipation, small size and compatible with the temperature sensors. The method is proposed to set each of the transistor channel length, for finding out the threshold voltage difference of the inverter each on the TIQ comparator. The design has an input range of 285 to 600 mV and 6-bit resolution output. The chip area of the designed ADC is 844,48 × 764,77 µm 2 and the power dissipation is 0,162 µW with 1,6 V supply voltage. Keywords: CMOS, Comparator, Flash ADC, Temperature Sensor Serijski izlazni impulsni ADC male snage u 0,18 µm CMOS postupkuIzvorni znanstveni članak U radu se predlaže jednostavan projekt impulsno analogno-digitalnog pretvarača (ADC) u 0,18 μm CMOS tehnologiji. Taj bi se pretvarač trebao koristiti u senzoru temperature, koji daje izlaz analognih podataka u rasponu od 360 mV do 560 mV. Sustav se sastoji od tri glavna bloka: threshold inverter quantization (TIQ) -komparatora, kodnog uređaja (kodera) i parallel input serial output (PISO) registra. Svrha je projekta dobiti impulsni ADC s malim gubitkom energije, malih dimenzija i kompatibilnim sa senzorima temperature. Ovom bi se metodom trebala podesiti dužina svakog kanala tranzistora u svrhu pronalaženja razlike u ulaznom naponu pretvarača na TIQ komparatoru. Projektom se predviđa ulazni raspon od 285 do 600 mV i izlaz rezolucije 6-bita. Površina čipa projektiranog ADC je 844,48 × 764,77 µm 2 a gubitak energije iznosi 0,162 µW uz napajanje od 1,6 V.

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A 6-fJ/conversion-step 200-kSps asynchronous SAR ADC with attenuation capacitor in 130-nm CMOS

Brenna

Bonfanti

2014

Analog Integr Circ Sig Process

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A 1.2 V 8-bit 1 MS/s SAR ADC with Res–Cap segment DAC for temperature sensor in LTE

Cited by 4 publications

References 13 publications

<b>Design of a low-power flash analog-to-digital converter chip for temperature sensors in 0.18 µm CMOS process

<b>Design of a low-power flash analog-to-digital converter chip for temperature sensors in 0.18 µm CMOS process

A low power serial output flash ADC in 0,18 µm CMOS process

A 6-fJ/conversion-step 200-kSps asynchronous SAR ADC with attenuation capacitor in 130-nm CMOS

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