A 1.3 Tb/s parallel optics VCSEL link

Hasharoni, Kobi; Benjamin, Stacy; Geron, Amir; Stepanov, S.; Katz, Gideon; Epstein, Itai; Margalit, N.; David, M; Mesh, Michael

doi:10.1117/12.2038073

Cited by 7 publications

(3 citation statements)

References 6 publications

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“…This can be carried out if the optical interconnect is co-packaged with the switch ASIC (Figure 1c). Hybrid integration (Figure 1d) with the III-V optoelectronics assembled directly onto the ASIC was demonstrated to be a very promising approach, notably enabling o triple the number of chip I/O ports [6]. However, several challenges need to be overcome before it can be fully implemented, mainly related to its high complexity and thus relatively high cost.…”

Section: System Architecturementioning

confidence: 99%

Co-Package Technology Platform for Low-Power and Low-Cost Data Centers

Papatryfonos

Selviah

Maman³

et al. 2021

Applied Sciences

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We report recent advances in photonic–electronic integration developed in the European research project L3MATRIX. The aim of the project was to demonstrate the basic building blocks of a co-packaged optical system. Two-dimensional silicon photonics arrays with 64 modulators were fabricated. Novel modulation schemes based on slow light modulation were developed to assist in achieving an efficient performance of the module. Integration of DFB laser sources within each cell in the matrix was demonstrated as well using wafer bonding between the InP and SOI wafers. Improved semiconductor quantum dot MBE growth, characterization and gain stack designs were developed. Packaging of these 2D photonic arrays in a chiplet configuration was demonstrated using a vertical integration approach in which the optical interconnect matrix was flip-chip assembled on top of a CMOS mimic chip with 2D vertical fiber coupling. The optical chiplet was further assembled on a substrate to facilitate integration with the multi-chip module of the co-packaged system with a switch surrounded by several such optical chiplets. We summarize the features of the L3MATRIX co-package technology platform and its holistic toolbox of technologies to address the next generation of computing challenges.

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Section: System Architecturementioning

confidence: 99%

Co-Package Technology Platform for Low-Power and Low-Cost Data Centers

Papatryfonos

Selviah

Maman³

et al. 2021

Applied Sciences

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“…For this purpose, the dReDBox 1 (Disaggregated Recursive Datacentre-in-a-Box) project took the challenge [25] of breaking the server boundaries aiming to materialize the concept of disaggregation, benefiting itself from the technological improvements of the interconnection components such as low-latency all-optical switches [16] [17]. The main idea of the dReDBox architecture is to dilute the base unit of data centers through a core of high-speed, low latency optoelectronic fabric that gathers together physically distant components in terms of bandwidth and latency.…”

Section: Introductionmentioning

confidence: 99%

Diluting the Scalability Boundaries: Exploring the Use of Disaggregated Architectures for High-Level Network Data Analysis

Vega

Zazo²,

Meyer

et al. 2017

2017 IEEE 19th International Conference on High Performance Computing and Communications; IEEE 15th International Conference On

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Traditional data centers are designed with a rigid architecture of fit-for-purpose servers that provision resources beyond the average workload in order to deal with occasional peaks of data. Heterogeneous data centers are pushing towards more cost-efficient architectures with better resource provisioning. In this paper we study the feasibility of using disaggregated architectures for intensive data applications, in contrast to the monolithic approach of server-oriented architectures. Particularly, we have tested a proactive network analysis system in which the workload demands are highly variable. In the context of the dReDBox disaggregated architecture, the results show that the overhead caused by using remote memory resources is significant, between 66% and 80%, but we have also observed that the memory usage is one order of magnitude higher for the stress case with respect to average workloads. Therefore, dimensioning memory for the worst case in conventional systems will result in a notable waste of resources. Finally, we found that, for the selected use case, parallelism is limited by memory. Therefore, using a disaggregated architecture will allow for increased parallelism, which, at the same time, will mitigate the overhead caused by remote memory.

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“…1,2) In recent years, optical interconnects implemented in high-end routers have established optical-fiber links between multiple linecards within the router chassis. 3,4) Such new-generation routing systems are expected to achieve not only a high transmission bandwidth but also savings in system size and power consumption.…”

Section: Introductionmentioning

confidence: 99%

GaInAsP/silicon-on-insulator hybrid laser with ring-resonator-type reflector fabricated by N₂ plasma-activated bonding

Hayashi

Suzuki

Inoue

et al. 2016

Jpn. J. Appl. Phys.

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III–V/Si hybrid integration with direct bonding is an attractive method of realizing an electrophotonic convergence router with a small size and a low power consumption. Plasma-activated bonding (PAB) is an effective approach for reducing thermal stress during the bonding process because PAB achieves a high bonding strength with low-temperature annealing. This time, the fabrication of a GaInAsP/silicon-on-insulator (SOI) hybrid laser with Si ring-resonator-type reflectors was demonstrated by N2 PAB. By measuring the lasing spectra, we confirmed the reflective characteristics resulting from the cascaded Si ring resonators. We also investigated kink characteristics, which occur around the threshold current, of the current–light output (I–L) characteristics, and successfully approximated the kink characteristics by considering saturable absorption occurring at the III–V/Si taper tip. The taper structure was investigated in terms of a passive device as well as an active device, and a structure for eliminating saturable absorption was proposed.

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A 1.3 Tb/s parallel optics VCSEL link

Cited by 7 publications

References 6 publications

Co-Package Technology Platform for Low-Power and Low-Cost Data Centers

Co-Package Technology Platform for Low-Power and Low-Cost Data Centers

Diluting the Scalability Boundaries: Exploring the Use of Disaggregated Architectures for High-Level Network Data Analysis

GaInAsP/silicon-on-insulator hybrid laser with ring-resonator-type reflector fabricated by N₂ plasma-activated bonding

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A 1.3 Tb/s parallel optics VCSEL link

Cited by 7 publications

References 6 publications

Co-Package Technology Platform for Low-Power and Low-Cost Data Centers

Co-Package Technology Platform for Low-Power and Low-Cost Data Centers

Diluting the Scalability Boundaries: Exploring the Use of Disaggregated Architectures for High-Level Network Data Analysis

GaInAsP/silicon-on-insulator hybrid laser with ring-resonator-type reflector fabricated by N2 plasma-activated bonding

Contact Info

Product

Resources

About

GaInAsP/silicon-on-insulator hybrid laser with ring-resonator-type reflector fabricated by N₂ plasma-activated bonding