A 1:4 Active Power Divider for 5G Phased-Array Transmitters in 22nm CMOS FDSOI

Abstract

A CMOS broadband 1:4 active power divider is proposed in this paper. The power splitter can be used in Phased Array Transceivers at the Transmitter side. It is based on a cascode 1:4 current splitter and transmission lines. Compared to other passive power dividers and active power dividers, the proposed design exhibits 1-2 dB power gain and smaller area. The measured input 1dB compression point is 6 dB whereas the IIP3 is 7.2 dBm. The Noise Figure of the Power Divider is 10 dB at lower frequencies and 15 dB at 28 GHz. The measured results are performed across several chips. Realized in 22nm CMOS FDSOI from GF, the total power consumption is 29 mW from a 1 V power supply and the area occupied by the divider is 700µm x 600µm. A thorough analysis of the gain and noise of the divider is presented as well.