“…With the arrival of big data era, NAND Flash memory with large capacity, high bandwidth and high reliability is widely used, and the data transmission rate between NAND Flash memory and controller is also increasing [1,2,3,4,5,6,7,8,9,10,11,12]. Data transmission between NAND Flash memory and controller is realized by utilizing Non-Volatile double data rate (NV-DDR) interface which requires sampling data at the positive and negative edge of interface clock [1,2,3,4,5,6,7]. So the NV-DDR interface requires the interface clock with a 50% duty cycle.…”