A 1-Tb Density 4b/Cell 3D-NAND Flash on 176-Tier Technology with 4-Independent Planes for Read using CMOS-Under-the-Array

A Review of Cell Operation Algorithm for 3D NAND Flash Memory

“…Most major 3D NAND memory manufacturers, such as Samsung, SK Hynix, and Micron, began to produce TLC NAND products from 2015, and competition to improve program throughput of TLC operation has started to accelerate [11]. Regarding multi-plane operation, in the middle of 2010, two-plane architecture started to be used; now, four-plane operation has become the mainstream [30][31][32]. In addition, starting from a programming time of ~800 us in 2014, current TLC NAND products are required to operate at value of less than 400 us [6], as shown in Figure 1.…”

“…Therefore, the trade-off between the program performance and cell distribution must be carefully considered. On the other hand, T. Pekny et al suggested a dual verify scheme [31]. To simultaneously perform verification of two adjacent Vt levels in one verify operation, two different BL bias were applied from a page buffer circuit, wherein two distribution levels were verified in one WL step.…”

“…In 2D NAND, a two-plane architecture with 8 KB page size used to be the mainstream; however, as the field moved to 3D NAND, a two-plane architecture with 16 KB page size was adopted [47]. Currently, cell under array (CuA) technology has secured space for more page buffer circuits and sense amplifiers, and so four-plane architecture with 16 KB is applied to most 3D NAND products [30,31,46,63], as shown in Figure 10a; this parallel technology contributes to higher read and program performance [70]. For further improvement, an independent multi-plane read operation is proposed, in which each group of two or four planes can perform read operations independently and asynchronously on any block/page address, thereby improving system level read and write performances [69,71,72], as shown in Figure 10b.…”

Fabrication of a Hole‐Type Vertical Resistive‐Switching Random‐Access Array and Intercell Interference Induced by Lateral Charge Spreading

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The current most prevailing V-NAND comprises 176 layer-stacked devices, and 238 layer-stacked devices are already reported. [1][2][3][4] However, the strategy of increasing layer number to increase the memory density will see its limitation within a decade due to the tolerable stack height (≈15 µm). [5][6][7] Then, the remaining option is to decrease the height of the unit stack layer, but the risk of lateral charge spreading accompanies this strategy.

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