A 10-bit 10-MS/s single-ended asynchronous SAR ADC with CDAC boosting common-mode voltage and controlling input voltage range

Abstract

A capacitor digital-to-analog converter (CDAC), which boosts the common-mode voltage and controls the input voltage rang, is proposed to improve the dynamic range and linearity of a singleended successive approximation register (SAR) analog-to-digital converter (ADC). The 10-bit 10-MS/s single-ended asynchronous SAR ADC using the proposed CDAC is implemented by using a 180-nm CMOS process with a supply voltage of 1.8 V. Its active area and power consumption are 0.207 mm 2 and 2.29 mW, respectively. The measured DNL and INL are +0.93/−0.51 LSBs and +0.61/−0.81 LSBs, respectively. The measured ENOB is 9.04 bits for the analog input signal with Nyquist frequency.

A 10-bit 120MS/s SAR ADC using tri-switch sampling and VCM-stable switching scheme in 40-nm CMOS

“…Each owns specific characteristics in terms of sample rate, accuracy, etc. Featuring high power efficiency and low circuit complexity, asynchronous charge-redistributed SAR ADCs have become a popular choice for moderate-resolution and moderate-speed applications [16,17,18,19,20,21,22,23,24,25]. The monotonic switching scheme and top-plate sampling proposed in [16] dramatically reduce the average switching power and total capacitance.…”