A 110 MHz to 1.4 GHz Locking 40-Phase All-Digital DLL

Kim, Young-Sang; Lee, Seon-Kyoo; Park, Hong-June; Sim, Jae‐Yoon

doi:10.1109/jssc.2010.2092996

Cited by 30 publications

(10 citation statements)

References 13 publications

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“…Hence, a latch-based binary phase detector [9], shown in Fig. 6(a), is employed in the dither free PD instead of a flip-flop based binary phase detector.…”

Section: Mdf Pd (Multi Dither Free Phase Detector)mentioning

confidence: 99%

A Digital DLL with 4-Cycle Lock Time and 1/4 NAND-Delay Accuracy

Kim¹,

Jin²,

Chun³

et al. 2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This paper presents a fully digital delay locked loop (DLL) that can acquire lock in four clock cycles with a resolution of a 1/4 NAND-delay. The proposed DLL with a multi-dither-free phase detector acquires the initial lock in four clock cycles with 1/2 NAND-delay. Then, it utilizes a multi-dither-free phase detector, a region accumulator, and phase blenders, to improve the resolution to a 1/4 NANDdelay. The region accumulator which continuously steers the control registers and the phase blender, adaptively controls the tracking bandwidth depending on the amount of jitter, and effectively suppresses the dithering jitter. Fabricated in a 65 nm CMOS process, the proposed DLL occupies 0.0432 mm 2 , and consumes 3.7 mW from a 1.2-V supply at 2 GHz.Index Terms-Delay-locked loop, DLL, multi-ditherfree phase detector, fast lock, merged dual delay line, region accumulator

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“…Hence, a latch-based binary phase detector [9], shown in Fig. 6(a), is employed in the dither free PD instead of a flip-flop based binary phase detector.…”

Section: Mdf Pd (Multi Dither Free Phase Detector)mentioning

confidence: 99%

A Digital DLL with 4-Cycle Lock Time and 1/4 NAND-Delay Accuracy

Kim¹,

Jin²,

Chun³

et al. 2016

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

show abstract

“…In these systems, a local voltage-controlled oscillator (VCO), placed in a closed-loop configuration, generates the desired clock signal. In many cases, a PLL or DLL is used to generate the clock signal at the receiver, which is synchronized with the incoming data stream and is used for recovering the data bits [20][21][22][23][24][25][26][27]. Lock speed depends on the design, with DLLs being usually faster than PLLs.…”

Section: Related Workmentioning

confidence: 99%

A small fully digital open‐loop clock and data recovery circuit for wired BANs

Derogarian

Ferreira

Tavares

2015

Circuit Theory & Apps

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This paper proposes a new open-loop and low complexity (small size) fast-lock synchronization circuit for clock and data recovery in wearable systems. The system includes sensors embedded in textile and connected by conductive yarns. Synchronization is based on the open-loop selection of the correct phase of the receiver clock synchronously with the incoming signal. The clock generator of the receiver is an autonomous oscillator set to operate at the same nominal frequency. The circuit lock time is at most one clock cycle, faster than all methods based on phase-locked loops or delay-locked loops. The circuit can be used for baseband communication independently of the signal coding method used in the physical layer, making it suitable for many applications. The fully digital circuit (including non-return-to-zero inverted decoder) occupies 0.0022 in a 0.35 complementary metal-oxide semiconductor (CMOS) process, a smaller implementation than many existing circuits, and supports a maximum system clock frequency of 70 for a 35-data rate. Experimental results demonstrate that the proposed circuit robustly generates a synchronous clock for data recovery. The circuit is suitable for systems that tolerate some jitter but requires fast lock time, small size, and low energy consumption.

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“…Unfortunately, however, circuit realization through switched-capacitor array usually implies high design cost and large power consumption due to the need for a high-resolution analog comparator. Furthermore, large capacitor mismatches due to the usage of single threshold capacitance can lead to inaccuracies and requires as many as 3-4 non-overlapping phased clock signals, usually generated by a delay-locked loop circuit [29,30]. Layout design is also riddled with pitfalls that may complicate testing and compromise reliable operation.…”

Section: Basic Concepts and Functionalitymentioning

confidence: 99%

A mixed analog–digital fast hamming-weight filtering circuit using switched-capacitor arrays

Abdel-Hafeez

Parhami

Alhammouri

2015

Analog Integr Circ Sig Process

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Many circuit design applications rely on an intermediate sequence to carry a decision to the next circuit stage. The decision may be carried by a weighted pattern of N bits, with the weights being selected in a way that optimizes the circuit implementation or some aspect of performance. For example, when the weights are consecutive powers of 2 beginning with 1 = 2 0 , we have the standard binary representation. As another example, when all the weights are 1, we have the unary representation that encodes a value k by k asserted bits and N-k unasserted bits (a weightk bit vector of length N). In this paper, we present the design of a circuit that screens a unary representation to verify that the represented value falls between preset lower and upper limits l and u, passing through any string that represents a value in the interval [l, u] and outputting the all-0 s bit pattern otherwise. Our mixed analog-digital circuit implementation, based on switched-capacitor arrays, provides a decision output within a clock cycle of 4 ns for 16-bit unary representation, when realized with 0.15 lm TSMC technology. The latter results were obtained with normal, per-bit capacitance of 200 fF and single-clock-cycle operation. As an added benefit, our filtering circuit can form the basis for designing a cost-effective Hamming decoder circuit.

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A 110 MHz to 1.4 GHz Locking 40-Phase All-Digital DLL

Cited by 30 publications

References 13 publications

A Digital DLL with 4-Cycle Lock Time and 1/4 NAND-Delay Accuracy

A Digital DLL with 4-Cycle Lock Time and 1/4 NAND-Delay Accuracy

A small fully digital open‐loop clock and data recovery circuit for wired BANs

A mixed analog–digital fast hamming-weight filtering circuit using switched-capacitor arrays

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