A 12 bit 1 GS/s Dual-Rate Hybrid DAC With an 8 GS/s Unrolled Pipeline Delta-Sigma Modulator Achieving &gt; 75 dB SFDR Over the Nyquist Band

Su, Stephen Y. H.; Tsai, Tu-I; Sharma, Praveen Kumar; Chen, Mike Shuo-Wei

doi:10.1109/jssc.2014.2385752

Cited by 39 publications

(37 citation statements)

References 14 publications

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“…The performance limitations of TIDSM DACs are also investigated (Papers II, IV-V) [37][38][39]. Only very recently, another TIDSM based hybrid DAC has been also reported in [40] which indicates a growing interest in this topic. Figure 1-13 shows the achievable linearity for ∆Σ DACs and Nyquist DACs for various bandwidths [40].…”

Section: Organization and Scope Of Dissertationmentioning

confidence: 99%

“…Only very recently, another TIDSM based hybrid DAC has been also reported in [40] which indicates a growing interest in this topic. Figure 1-13 shows the achievable linearity for ∆Σ DACs and Nyquist DACs for various bandwidths [40]. This dissertation aims to increase the overlap between the ∆Σ DACs and Nyquist DACs by using TIDSMs.…”

Section: Organization and Scope Of Dissertationmentioning

confidence: 99%

“…Only the final combination part works at full sampling rate. Alternative terminology like poly-phase decomposition or loop-unrolling is also often used in literature instead of timeinterleaving (TI) [33,34,40,44]. …”

Section: Time-interleaved Dsm and Previous Workmentioning

confidence: 99%

“…Hence, logic is required after the decomposed integrator to compute the correct MSBs that drive the DAC. This logic requires more adders which result in further area and power consumption and has only recently been studied in [40].…”

Section: Time-interleaved Dsm and Previous Workmentioning

confidence: 99%

“…At the time of the start of this dissertation, [33] and [34] were the only two reported TIDSM high-speed implementations in the literature. Only very recently, another TIDSM has been reported in [40] and is an eight-channel 8 GS/s TI-MASH 1-1-1 DSM for a Nyquist-∆Σ hybrid DAC using an implementation that is based on Fig. 2-20.…”

Section: Time-interleaved Dsm and Previous Workmentioning

confidence: 99%

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Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

Bhide

2015

Linköping Studies in Science and Technology. Dissertations

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Digital-to-analog (D/A) converters (or DACs) are one the fundamental building blocks of wireless transmitters. In order to support the increasing demand for high-data-rate communication, a large bandwidth is required from the DAC. With the advances in CMOS scaling, there is an increasing trend of moving a large part of the transceiver functionality to the digital domain in order to reduce the analog complexity and allow easy reconfiguration for multiple radio standards. ∆Σ DACs can fit very well into this trend of digital architectures as they contain a large digital signal processing component and offer two advantages over the traditionally used Nyquist DACs. Firstly, the number of DAC unit current cells is reduced which relaxes their matching and output impedance requirements and secondly, the reconstruction filter order is reduced.Achieving a large bandwidth from ∆Σ DACs requires a very high operating frequency of many-GHz from the digital blocks due to the oversampling involved. This can be very challenging to achieve using conventional ∆Σ DAC architectures, even in nanometer CMOS processes. Time-interleaved ∆Σ (TIDSM) DACs have the potential of improving the bandwidth and sampling rate by relaxing the speed of the individual channels. However, they have received only some attention over the past decade and very few previous works been reported on this topic. Hence, the aim of this dissertation is to investigate architectural and circuit techniques that can further enhance the bandwidth and sampling rate of TIDSM DACs.The first work is an 8-GS/s interleaved ∆Σ DAC prototype IC with 200-MHz bandwidth implemented in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1-1 digital ∆Σ modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. Two-channel interleaving allows the use of a single clock for both the logic and the final multiplexing. This requires each channel to operate at half the sampling rate i.e. 4 GHz. This is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results from the prototype show that the DAC achieves 200-MHz bandwidth, −57-dBc IM3 and 26-dB SNDR, with a power consumption of 68-mW at 1-V digital and 1.2-V analog supplies. This architecture shows good potential for use in the transmitter baseband. While a good linearity is obtained from this DAC, the SNDR is found to iv be limited by the testing setup for sending high-speed digital data into the prototype.The performance of a two-channel interleaved ∆Σ DAC is found to be very sensitive to the duty-cycle of the half-rate clock. The second work analyzes this effect mathematically and presents a new closed-form expression for the SNDR loss of two-channel DACs due to the duty cycle error (DCE) for a noise transfer function (NTF) of (1 − z −1 ) n . It is shown that a low-order FIR filter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this filter is also developed. The...

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Section: Organization and Scope Of Dissertationmentioning

confidence: 99%

Section: Organization and Scope Of Dissertationmentioning

confidence: 99%

Section: Time-interleaved Dsm and Previous Workmentioning

confidence: 99%

Section: Time-interleaved Dsm and Previous Workmentioning

confidence: 99%

Section: Time-interleaved Dsm and Previous Workmentioning

confidence: 99%

See 3 more Smart Citations

Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

Bhide

2015

Linköping Studies in Science and Technology. Dissertations

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Redundancy‐bandwidth scalable techniques for signal‐independent element transition rates in high‐speed current‐steering DACs

Lai

Yang

2018

Circuit Theory & Apps

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This paper presents redundancy-bandwidth scalable techniques to deal with the intersymbol interference distortions for current-steering digital-to-analog converters in high-speed applications. A switching strategy that explores the use of redundant current sources is proposed to realize a signal-independent element transition rate, ie, the number of switching activities during the transition of successive sampling clock cycles. With a certain number of redundant current sources, this strategy significantly reduces the intersymbol interference distortions without oversampling operation or causing signal attenuation, which makes it appealing for high-speed applications. As analyzed in this paper, the number of required redundant current sources is scalable for different bandwidth requirement in specific applications, leading to 3 redundancy-bandwidth scalable trade-offs between the cost from redundant current sources and the high-dynamic-range bandwidth. In implementation, we propose a customdesigned decoder, named as the overlap-controlled data-weighted averaging (OC-DWA). Compared with the existing similar-purpose designs, the proposed OC-DWA decoder realizes the current sources selection with a simple barrel rotator, which is of much lower hardware complexity and energy consumption.Simulations of a digital-to-analog converter with this decoder exhibit an enhanced dynamic range over the entire Nyquist band, which verifies the redundancy-bandwidth scalability of the proposed techniques.

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Mismatch error compensation of hybrid CS‐DAC to achieve high figure of merit utilizing on‐chip self‐healing assisted swap‐enabled randomization technique

Samanta,

Sarkar

2023

Circuit Theory & Apps

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SummaryThe process and design variations during fabrication generate random mismatch‐induced nonlinearities in Current steering DACs (CS‐DACs), which are the main reason for performance degradation. Considering this, a mismatch error compensation method is highly desirable to boost both static and dynamic performances for the wide‐band CS‐DACs. To address this issue, an on‐chip self‐healing assisted swap‐enabled randomization technique (SASR) is proposed in this work for the Nyquist band CS‐DAC structures. This paper presents a robust hybrid CS‐DAC architecture to enhance both static and dynamic performances. The partial self‐healing method measures and recovers the mismatch current of the current cells. Further, to reduce the mismatch‐based nonlinear distortions, swap‐enabled randomization technique is adopted. This enhances the high‐frequency spurious‐free dynamic range (SFDR) values by mitigating inter and intra‐segment mismatch errors. A higher figure of merit (FoM) is obtained for 10‐bit CS‐DAC architecture utilizing the proposed SASR technique compared with state‐of‐the‐art DACs, which indicates the suitability for higher precision and high‐speed CS‐DAC structures.

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A 12 bit 1 GS/s Dual-Rate Hybrid DAC With an 8 GS/s Unrolled Pipeline Delta-Sigma Modulator Achieving > 75 dB SFDR Over the Nyquist Band

Cited by 39 publications

References 14 publications

Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

Redundancy‐bandwidth scalable techniques for signal‐independent element transition rates in high‐speed current‐steering DACs

Mismatch error compensation of hybrid CS‐DAC to achieve high figure of merit utilizing on‐chip self‐healing assisted swap‐enabled randomization technique

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