A 12Bit 200Msps Spilt-Based Pipeline ADC Design

Abstract

Abstract-This paper presents a 12bit 200Msps pipeline ADC fabricated in TSMC 0.18um CMOS technology. For high resolution pipeline ADC design, the operation speed is limited by sampling capacitance load of OTA inside the ADC. The proposed ADC is realized in split-based pipeline architecture, sampling capacitance of ADC is separated into two channels. Each channel only has half capacitance, which reduce capacitive loading of OTAs in each channel and realize high speed operation of the ADC. The ADC achieves an SNDR of 64.7dB, SFDR of 86.3dB with analog input frequency of 10MHz, sampling frequency of 100MHz and differential amplitude of 1.25Vpp without digital calibration. The power dissipation of ADC is 356mW at 1.8V supply.Index Terms-OTA, pipeline ADC, split-based. I. INTRODUCTIONCMOS ADCs with sampling rate more than 100Msps and resolution more than 10bit are widely used in optical communication system, wireless and wired broadband communication systems [1]. Pipeline is the appropriate architecture widely used in this class of ADCs for its reasonable trade-offs among sampling rate, resolution and power. To realize the high sampling rate and high resolution pipeline ADC, the OTA to drive large sampling capacitance inside MDAC becomes the bottleneck which limits the sampling rate of ADC. Split ADC architecture is the useful method to reduce the capacitance need to be driven by OTA in pipeline ADC [2]. Split-based pipeline ADC consists of 2 independent ADCs with the same circuit structure which shares a same SHA [3]. The block diagram of traditional split ADC is shown in Fig. 1, The output code of ADC (A) and ADC(B) are X A and X B respectively. By average calculation, the final output code of the ADC can be written as Eq. 1, and difference between outputs of 2 ADCs can be written as Eq. 2.