A 135Mb/s DVB-S2 compliant codec based on 64800b LDPC and BCH codes

Urard, Pascal; Yeo, E.; Paumier, L.; Georgelin, P.; Michel, Thierry; Lebars, V.; Lantreibecq, E.; Gupta, B.

doi:10.1109/isscc.2005.1494061

Cited by 44 publications

(27 citation statements)

References 5 publications

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“…We implemented DVB-S2 in hardware as described in [20,21]. Figure 13 shows the reduction of power consumption after the novel algorithm is applied.…”

Section: Implementation Resultsmentioning

confidence: 99%

An adaptive low-power LDPC decoder using SNR estimation

Park

Chung

2011

J Wireless Com Network

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Owing to advancement in 4 G mobile communication and mobile TV, the throughput requirement in digital communication has been increasing rapidly. Thus, the need for efficient error-correcting codes is increasing. Furthermore, since most mobile devices operate with limited battery power, low-power communication techniques are attracting considerable attention lately. In this article, we propose a novel low-power, low-density parity check (LDPC) decoder. The LDPC code is one of the most common error-correcting codes. In mobile TV, SNR estimation is required for the adaptive coding and modulation technique. We apply the SNR estimation result to the proposed LDPC decoding to minimize power consumption due to unnecessary operations. The SNR estimation value is used for predicting the iteration count until the completion of the successful LDPC decoding. When the SNR value is low, we omit computing the parity check and the tentative decision. We implemented the proposed decoder which is capable of adaptively skipping unnecessary operations based on the SNR estimation. The power consumption was measured to show the efficiency of our approach. We verified that, by using our proposed method, power consumption is reduced by 10% for the SNR range of 1.5-2.5 dB.

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“…We implemented DVB-S2 in hardware as described in [20,21]. Figure 13 shows the reduction of power consumption after the novel algorithm is applied.…”

Section: Implementation Resultsmentioning

confidence: 99%

An adaptive low-power LDPC decoder using SNR estimation

Park

Chung

2011

J Wireless Com Network

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“…The bit-serial fully-parallel architecture proposed in this work addresses these concerns by reducing both interconnect complexity and logic area. Although the needs of applications specifying long block-length and low-throughput LDPC codes (such as DVB-S2 [4]) can be met with lower levels of parallelism (e.g., [24], [26], [23], [22]), a fully parallel decoder is preferable for applications such as 10GBase-T which use a medium-size LDPC code (e.g., 2048 bit) and require multi-Gb/s decoding throughput. We reported on a fabricated 0.13-m CMOS bit-serial fully-parallel LDPC decoder and show the effect of the proposed techniques.…”

Section: Discussionmentioning

confidence: 99%

Power Reduction Techniques for LDPC Decoders

Darabiha

Carusone

Kschischang

2008

IEEE J. Solid-State Circuits

114

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Abstract-This paper investigates VLSI architectures for lowdensity parity-check (LDPC) decoders amenable to low-voltage and low-power operation. First, a highly-parallel decoder architecture with low routing overhead is described. Second, we propose an efficient method to detect early convergence of the iterative decoder and terminate the computations, thereby reducing dynamic power. We report on a bit-serial fully-parallel LDPC decoder fabricated in a 0.13-m CMOS process and show how the above techniques affect the power consumption. With early termination, the prototype is capable of decoding with 10.4 pJ/bit/iteration, while performing within 3 dB of the Shannon limit at a BER of 10 5 and with 3.3 Gb/s total throughput. If operated from a 0.6 V supply, the energy consumption can be further reduced to 2.7 pJ/bit/iteration while maintaining a total throughput of 648 Mb/s, due to the highly-parallel architecture. To demonstrate the applicability of the proposed architecture for longer codes, we also report on a bit-serial fully-parallel decoder for the (2048, 1723) LDPC code in 10GBase-T standard synthesized with a 90-nm CMOS library.

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“…We depicted the standard limit at 1 dB from the Shannon limit in E b /N 0 for rate 2/3. Simulations show the robustness of Table IV shows the number of bits for the main memory units in the latest published DVB-S2 decoder IPs [9], [13], [14]. Note that no information is provided on the ROM memories that store the matrices for every rate.…”

Section: Vi-a Synthesismentioning

confidence: 99%

Architecture and Finite Precision Optimization for Layered LDPC Decoders

Marchand

Conde-Canencia

Boutillon

2011

J Sign Process Syst

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Layered decoding is known to provide efficient and highthroughput implementation of LDPC decoders. In the practical hardware implementation of layered decoders, the performance is strongly affected by quantization. The finite precision model determines the area of the decoder, which is mainly composed of memory, especially for long frames. To be specific, in the DVB-S2,-T2 and -C2 standards, the memory can occupy up to 70% of the total area. In this paper, we focus our attention on the optimization of the number of quantization bits. Message saturation and memory size optimization are considered for the case of a DVB-S2 decoder. We show that the memory area can be reduced by 28% compared to the state-of-the-art, without performance loss.Index Terms-Low-density parity-check (LDPC) code, layered decoding, VLSI implementation, DVB-S2.

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A 135Mb/s DVB-S2 compliant codec based on 64800b LDPC and BCH codes

Cited by 44 publications

References 5 publications

An adaptive low-power LDPC decoder using SNR estimation

An adaptive low-power LDPC decoder using SNR estimation

Power Reduction Techniques for LDPC Decoders

Architecture and Finite Precision Optimization for Layered LDPC Decoders

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