A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET

Kim, Gain; Kossel, Marcel; Cevrero, Alessandro; Özkaya, İlter; Burg, Andreas; Toifl, Thomas; Leblebici, Yusuf; Kull, Lukas; Luu, Danny; Braendli, Matthias; Menolfi, Christian; Francese, Pier Andrea; Yueksel, Hazar; Aprile, Cosimo; Morf, Thomas

doi:10.1109/jssc.2019.2938414

Cited by 32 publications

(5 citation statements)

References 16 publications

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“…The performance of the mixed-signal scheme of Section III-C is investigated in typical hierarchical ultra high-speed TI-ADCs such as those used in high speed receivers [42], [43], [46]. This hierarchical TI-ADC architecture organizes the T&H in two or more ranks with a high number of sub-ADCs.…”

Section: B Mixed-signal Compensation Of Ti-adc With Highly Interleave...mentioning

confidence: 99%

On the Application of Error Backpropagation to the Background Calibration of Time Interleaved ADC for Digital Communication Receivers

Solis,

Reyes,

Morero

et al. 2020

Preprint

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This paper introduces a backpropagation-based technique for the calibration of the mismatch errors of timeinterleaved analog to digital converters (TI-ADCs). This technique is applicable to digital receivers such as those used in coherent optical communications. The error at the slicer of the receiver is processed using a modified version of the well known backpropagation algorithm from machine learning. The processed slicer error can be directly applied to compensate the TI-ADC mismatch errors with an adaptive equalizer, or it can be used to digitally estimate and correct said mismatch errors using analog techniques such as delay cells and programmable gain amplifiers (PGA). The main advantages of the technique proposed here compared to prior art are its robustness, its speed of convergence, and the fact that it always works in background mode, independently of the oversampling factor and the properties of the input signal, as long as the receiver converges. Moreover, this technique enables the joint compensation of impairments not addressed by traditional TI-ADC calibration techniques, such as I/Q skew in quadrature modulation receivers. Simulations are presented to demonstrate the effectiveness of the technique, and low complexity implementation options are discussed.

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Section: B Mixed-signal Compensation Of Ti-adc With Highly Interleave...mentioning

confidence: 99%

On the Application of Error Backpropagation to the Background Calibration of Time Interleaved ADC for Digital Communication Receivers

Solis,

Reyes,

Morero

et al. 2020

Preprint

View full text Add to dashboard Cite

show abstract

“…In time-interleaved structures, [30]- [37], in simple terms, L (8 to 48) ADCs acquire the input signal at the same rate (up to 5 GSps), with a time-offset equal to 1/L of the sample period, so that the aggregate throughput is L times the sample rate of the individual ADCs. The general structure of the processing chain, for a single channel, of a DSO is shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

Real-Time Downsampling in Digital Storage Oscilloscopes With Multichannel Architectures

Napoli

Zacharelos

D’Arco

et al. 2021

IEEE Trans. Circuits Syst. I

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Digital Storage Oscilloscopes (DSOs) conjugate high performance with large number of features and flexibility. The basic structure, based on fast Analog to Digital Converter (ADC) and memory, is augmented with several components for channel matching and bandwidth improvement, and processors that provide visualization, frequency processing, jitter and stability measurement, etc. Unfortunately, fine resolution in sample rate selection is not available, such that for several applications the user must run complex measurement procedures that require data download and offline processing. The paper proposes a dedicated digital circuit that offers fine control of the time-base by real time downsampling the input stream at an almost arbitrary sampling rate. The proposed circuit implements a series of operations involving real-time data filtering, defragmentation and packing, which are not considered by alternative approaches, like those based on polyphase filters, that offer very limited choices for the sampling rate. The circuit is designed to work in conjunction with the highest performance DSOs that use a multichannel architecture. Design rules for circuit design are provided together with implementation results in 14nm FinFET technology. When designed for an architecture with 64 channels with 8bit input samples the circuit works in real time with a sampling rate of 220 GSps running at 3.42 GHz, with a silicon footprint of 0.17 mm 2 and a power dissipation of 0.85W.

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“…Then the signal processing is implemented by digital circuit, including the slicers, the DFE and so on. Thus, these receivers are widely used because of their design flexibility [3,4,5,6,7,8,9,10,11,12]. However, the design process limits the speed of receivers.…”

Section: Introductionmentioning

confidence: 99%

A 56-Gbps PAM4 amplitude-rectification-based receiver with threshold adaptation and 1-tap DFE

Han

Wang

2021

IEICE Electron. Express

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This paper presents a 56-Gbps four-level pulse amplitude modulation (PAM4) quarter-rate receiver based on amplitude rectification. Compared with the conventional three-comparator structure, the PAM4 signal is converted into a 2-digit gray-code rather than a 3-digit thermometer-code. The amplitude is detected to decode the least significant bit (LSB), which allows the proposed receiver to use significantly less power by reducing the number of comparators. An inverter-based common-mode voltage stabilization circuit (CVSC) is proposed to reduce the effect of common-mode level changes as the amplitude is determined. To minimize the feedback delay, the 2-digit gray-code is fed back to DFE's summer directly. By reducing the digit of the feedback signal, the power will be further reduced as the DFE tap increases. The device consumes 83.5 mW over a 55-nm process.

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A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET

Cited by 32 publications

References 16 publications

On the Application of Error Backpropagation to the Background Calibration of Time Interleaved ADC for Digital Communication Receivers

On the Application of Error Backpropagation to the Background Calibration of Time Interleaved ADC for Digital Communication Receivers

Real-Time Downsampling in Digital Storage Oscilloscopes With Multichannel Architectures

A 56-Gbps PAM4 amplitude-rectification-based receiver with threshold adaptation and 1-tap DFE

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