A 16Kb SRAM with Programmable Replica Bitlines for Dynamic Voltage Scaling Systems

Abstract

The SRAM applied to dynamic voltage scaling systems has a problem that the differential voltage of the bitlines (ΔVBL) increases as the supply voltage rises with the conventional replica bitlines technique, and the increased ΔVBL degrades the SRAM performance and dissipates more power. In this paper, a programmable replica bitlines technique is presented to resolve the problem. With the new technique we acquired bitline discharge time reduction up to 25.3% at the cost of 0.6% area penalty in a 16Kb SRAM. The 16Kb SRAM test chip is fabricated by using 65nm low leakage technology. Testing results show that the maximum operational frequency of the SRAM is improved from 4.3% to 9.5% under the voltage range of 0.8V~1.4V comparing with the conventional one. The operating frequency of the SRAM with proposed technique is from 440MHz at 0.8V to 1.62GHz at1.4V.