A 19-bit low-power multibit sigma-delta ADC based on data weighted averaging

Abstract

This paper describes a low-power multibit sigma-delta analog-to-digital converter (ADC) which achieves 19-b resolution. Multibit quantization and feedback within a sigma-delta loop are shown to provide a power-efficient solution for high-resolution converters. As the linearity of the digital-toanalog converter (DAC) in the feedback path is a critical issue, a comparison of different DAC solutions is made demonstrating the efficiency of the data weighted averaging algorithm. An implementation of this technique within a monolithic sigma-delta ADC is then described. The whole chip, including the digital decimation filter, consumes only 2.7 mW for an 800-Hz output rate. The resolution and linearity improvement brought by data weighted averaging is confirmed by measurements.

A 15‐MHz bandwidth double sampling MASH25b‐15b sigma‐delta modulator with DEM for multibit DACs

“…The power consumptions of all the designs quoted in the table covers just the modulators, ie, without the digital decimation filters. The figure of merit (FOM) used for the comparison is defined as As shown in the table, the FOM of this work is 30.7 fJ/conv. for 15‐MHz bandwidth and 112.3‐fJ/conv.…”

“…This nonlinearity will finally deteriorate the SNDR and SFDR performance of the modulator . Most of the published literatures employ conditional randomization dynamic element matching (DEM) or data weighted averaging (DWA) for the multibit DACs . The first scheme simply employs a pseudorandom noise (PRN) code generator to make the thermometric selection of the DAC unit cells to be randomized.…”

“…7 Most of the published literatures employ conditional randomization dynamic element matching (DEM) or data weighted averaging (DWA) for the multibit DACs. [17][18][19] The first scheme simply employs a pseudorandom noise (PRN) code generator to make the thermometric selection of the DAC unit cells to be randomized. However, mismatch noise in the signal band is not shaped, and suppression is seriously limited.…”

Continuous-Time Sigma-Delta A/D Conversion

“…Actually, there have been many publications dealing with techniques to achieve the linearity requirements, based on design consideration [67] as well as digital or analog correction and linearization techniques [4,8,55,57,63,68,70,107,185,[211][212][213]. However, all of these possibilities make use of rather complex circuitry, causing an increase of area and power consumption as well as switching activity.…”

“…During the last 25 years, a large amount of Σ∆ modulator architectures has been proposed, e.g., [2,19,36,54,55,107,124,175,185]. The main objective of all these schemes is the reduction of the quantization noise within the baseband.…”