A 2.17-mW Acoustic DSP Processor With CNN-FFT Accelerators for Intelligent Hearing Assistive Devices

Lee, Yu-Chi; Chi, Tai-Shih; Yang, Chia-Hsiang

doi:10.1109/jssc.2020.2987695

Cited by 15 publications

(19 citation statements)

References 32 publications

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“…There is a trend towards algorithms, that are computationally more demanding. In recent years, algorithms for machine learning and deep learning [40,44,52] and binaural processing algorithms [46] are used. Recently proposed algorithms of this kind [57,67,69], of which no implementation details on a hearing aid processor are known, are not listed in Table 1.…”

Section: Algorithms For Hearing Aid Devicesmentioning

confidence: 99%

“…Using the same hardware accelerator for different audio signal processing tasks is also applied in other related work. In [40], an arithmetic unit with a dual MAC and butterfly unit can operate either in FFT mode or in CNN mode. By sharing hardware resources, 42% of hardware complexity can be saved.…”

Section: Asips With Hardware Acceleratorsmentioning

confidence: 99%

“…This also applies to the FIR filter accelerators presented in [4,51]. The accelerators presented in [4-6, 9, 25, 33, 63] are more complex and specific, because they implement complete algorithms, such as noise reduction (NR), feedback cancellation (FBC) or [40] Convolutional neural networks (CNN) and fast Fourier transform (FFT) accelerators for speech enhancement Pu et al [54] Streaming DSP for voice code word detection Gerlach et al [19] Co-processors for hyperbolic and trigonometric functions Lin et al [41] Noise reduction (NR) accelerator Lin et al [41] Multiply-accumulate (MAC) unit accelerator Lin et al [41] Fast Fourier transform (FFT) accelerator [4-6, 9, 25, 33, 63] Analysis filter bank (AFB) accelerator [4-6, 9, 25, 33, 63] Noise reduction (NR) accelerator [4-6, 9, 25, 33, 63] Feedback cancellation (FBC) accelerator [4-6, 9, 25, 33, 63] Wide dynamic range compression (WDRC) accelerator…”

Section: Asips With Hardware Acceleratorsmentioning

confidence: 99%

“…The wireless control part of the analog hearing aid, which presented in [12], is based on a dual tone multi frequency (DTMF) receiver, occupies 1.16×4.6 mm 2 , which is 16% of the total chip size Figure 10 Supply voltages of commercial and research hearing aids. [71] 0.60 V 1.00 V 90 nm CMOS Wei et al [72] 0.60 V 1.00 V 90 nm CMOS Lee et al [40] 0.60 V 0.90 V 40 nm CMOS Pu et al [54] 0.55 V 1.05 V 28 nm CMOS of 5.7×4.9 mm 2 . The silicon area of a hearing aid may be pad limited.…”

Section: Silicon Areamentioning

confidence: 99%

“…Neuteboom et al [49,50] 0.85 kB 0.368 kB instruction RAM, 0.096 kB data RAM and 0.384 kB coefficient RAM Paker et al [51] 1.23 kB 0,62 kB data memory for mini-cores, 0,438 kB instruction memory and 0,172 kB coefficient memory Chang et al [4] 5.00 kB 4 processing elements (PEs) with 512 B instruction memory, 512 B shared memory for inter-PE communication and 2.5 kB local memory Jia et al [25] 6.00 kB 6 kB data memory Moller et al [47] 22.50 kB 6,125 kB RAM and 16,375 kB ROM Mosch et al [48] 68.00 kB 4 kB instruction ROM and 64 kB DSP parameter RAM [2,62,63] 110.00 kB 6 separate logical memory banks, 24-bit data memory, 32-bit DSP instruction memory Gerlach et al [19] 140.00 kB 28 SRAMs, 65 kB instruction memory, 57 kB data memory and 16 kB audio interface memory Lee et al [40] 327.00 kB 4 processing cluster, each with 64 kB for the CNNs and 2 kB for the FFT accelerators the analog size of 2.77 mm 2 the area of the SRAM is 14% of the total chip size for a 130 nm ASIC technology. The memory size depends on the complexity and type of the audio processing algorithms.…”

Section: Work Total Detailsmentioning

confidence: 99%

See 4 more Smart Citations

A Survey on Application Specific Processor Architectures for Digital Hearing Aids

Gerlach

Payá-Vayá

Blume

2021

J Sign Process Syst

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On the one hand, processors for hearing aids are highly specialized for audio processing, on the other hand they have to meet challenging hardware restrictions. This paper aims to provide an overview of the requirements, architectures, and implementations of these processors. Special attention is given to the increasingly common application-specific instruction-set processors (ASIPs). The main focus of this paper lies on hardware-related aspects such as the processor architecture, the interfaces, the application specific integrated circuit (ASIC) technology, and the operating conditions. The different hearing aid implementations are compared in terms of power consumption, silicon area, and computing performance for the algorithms used. Challenges for the design of future hearing aid processors are discussed based on current trends and developments.

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Section: Algorithms For Hearing Aid Devicesmentioning

confidence: 99%

Section: Asips With Hardware Acceleratorsmentioning

confidence: 99%

Section: Asips With Hardware Acceleratorsmentioning

confidence: 99%

Section: Silicon Areamentioning

confidence: 99%

Section: Work Total Detailsmentioning

confidence: 99%

See 3 more Smart Citations

A Survey on Application Specific Processor Architectures for Digital Hearing Aids

Gerlach

Payá-Vayá

Blume

2021

J Sign Process Syst

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Number Systems for Deep Neural Network Architectures

Alsuhli,

Sakellariou,

Saleh

et al. 2024

Synthesis Lectures on Engineering, Science, and Technology

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Quantum computing is an emerging technology on the verge of reshaping industries, while simultaneously challenging existing cryptographic algorithms. FALCON, a recent standard quantum-resistant digital signature, presents a challenging hardware implementation due to its extensive non-integer polynomial operations, necessitating FFT over the ring Q[x]/(x n +1). This paper introduces an ultra-low power and compact processor tailored for FFT/IFFT operations over the ring, specifically optimized for FALCON applications on resource-constrained edge devices. The proposed processor incorporates various optimization techniques, including twiddle factor compression and conflict-free scheduling. In an ASIC implementation using a 22 nm GF process, the proposed processor demonstrates an area occupancy of 0.15 mm 2 and a power consumption of 12.6 mW at an operating frequency of 167 MHz. Since a hardware implementation of FFT/IFFT over the ring is currently non-existent, the execution time achieved by this processor is compared to the software implementation of FFT/IFFT of FALCON on a Raspberry Pi 4 with Cortex-A72, where the proposed processor achieves a speedup of up to 2.3×. Furthermore, in comparison to dedicated state-of-the-art hardware accelerators for classic FFT, this processor occupies 42% less area and consumes 83% less power, on average. This suggests that the proposed hardware design offers a promising solution for implementing FALCON on resource-constrained devices.

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