A 2.23 ps RMS jitter 3 μs fast settling ADPLL using temperature compensation PLL controller

Abstract

This report describes an all-digital phase-locked loop (ADPLL) with temperature-compensated settling time reduction. The novelty of this work is autonomous oscillation control word estimation without a look-up table or memory circuits. The proposed ADPLL includes a multi-phase oscillator as a digitally controlled oscillator (DCO). Digital timing error correction circuits are integrated to minimize the settling time that is degraded by phase conversion error. The ADPLL is fabricated using a 65 nm CMOS process. The test chip occupies 0.27 × 0.36 mm 2 . It achieves 2.23 ps RMS jitter and -224 dB FoM at 2.4 GHz output frequency with 8.85 mW power dissipation. Measurement results show that the 47% settling time is reduced by the proposed estimation block. The average settling time at 25 °C is 3 μs. I. 978-1-4799-4242-8/14/$31.00 c 2014 IEEE

A General gm/Id Temperature-Aware Design Methodology Using 180 nm CMOS up to 250 °C

“…where y is a vector of the circuit parameters with dimensions; a a vector of rational numbers; and π a vector of unit-less quantities; N and M are such N + M is the total number of parameters of x. Intuitively, (9) shows that the equation arriving at parameter P with a specific unit must have the same unit as P. This unit equality can only be achieved with the combination of rational powers of the parameters since, for example, exp (1 [V ]) has no defined unit. Therefore, the equation of P must have the form described by (9) where the product must have the same unit of P , and g must be dimensionless.…”

“…However, the analyzed temperature range is limited to 80 • C. Besides, passive inductors and the high values of resistors and capacitors are a limiting factor for certain technology nodes and considerably increase the silicon surface. In [9], a PLL with a digital-controlled oscillator is proposed with an external calibration circuit implement on an FPGA to compensate the temperature drift. Published works often rely on wide-bandgap transistors or feedback control systems to stabilize the VCO, increasing power consumption and silicon area.…”

A fast lock-in all-digital phase-locked loop in 40-nm CMOS technology

“…Fast lock-in ADPLLs [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,18,19,20,21] have been developed and applied in biomedical electronic devices, wireless devices with frequency hopping, spread spectrum clock generators, and implantable medical devices. These applications require reduction in standby power consumption and rapid frequency switching.…”