A 2.48Gb/s FPGA-based QC-LDPC decoder: An algorithmic compiler implementation

Mhaske, Swapnil; Uliana, David; Kee, Hojin; Ly, Tai; Aziz, Ahsan; Spasojević, Predrag

doi:10.1109/sarnof.2015.7324649

Cited by 10 publications

(1 citation statement)

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“…On account of the scalability and reconfigurability of the decoder architecture in [37], it is possible to achieve high-throughput by employing multiple decoder cores in parallel as detailed in [38]. As shown in Figure 11, the encoded bit stream is packetized into frames of equal size and distributed for decoding in a round-robin manner to the cores operating in parallel.…”

Section: Case Study: a 248 Gb/s Qc-ldpc Decoder On The Xilinxmentioning

confidence: 99%

FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis

Mhaske

Kee

et al. 2017

International Journal of Reconfigurable Computing

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We propose strategies to achieve a high-throughput FPGA architecture for quasi-cyclic low-density parity-check codes based on circulant-1 identity matrix construction. By splitting the node processing operation in the min-sum approximation algorithm, we achieve pipelining in the layered decoding schedule without utilizing additional hardware resources. High-level synthesis compilation is used to design and develop the architecture on the FPGA hardware platform. To validate this architecture, an IEEE 802.11n compliant 608 Mb/s decoder is implemented on the Xilinx Kintex-7 FPGA using the LabVIEW FPGA Compiler in the LabVIEW Communication System Design Suite. Architecture scalability was leveraged to accomplish a 2.48 Gb/s decoder on a single Xilinx Kintex-7 FPGA. Further, we present rapidly prototyped experimentation of an IEEE 802.16 compliant hybrid automatic repeat request system based on the efficient decoder architecture developed. In spite of the mixed nature of data processing-digital signal processing and finite-state machines-LabVIEW FPGA Compiler significantly reduced time to explore the system parameter space and to optimize in terms of error performance and resource utilization. A 4x improvement in the system throughput, relative to a CPU-based implementation, was achieved to measure the error-rate performance of the system over large, realistic data sets using accelerated, in-hardware simulation.

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Section: Case Study: a 248 Gb/s Qc-ldpc Decoder On The Xilinxmentioning

confidence: 99%