A 2.5 V broadband multi-bit ΣΔ modulator with 95 dB dynamic range

Vleugels, K.; Rabii, Shahriar; Wooley, B.A.

doi:10.1109/isscc.2001.912541

Cited by 20 publications

(20 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The signal bandwidth is 2 MHz. A design has been reported [4] which consumes 90 mW in the analog circuits to attain 95 dB DR and 90 dB peak SNR.…”

Section: Resultsmentioning

confidence: 99%

“…The yield optimizations have been conducted assuming a 1% (fair capacitor/capacitor matching) coefficient-to-coefficient mismatch for single-loop architectures and a 0.5% (good capacitor/capacitor matching) for cascaded architectures, based on the properties of the technologies in the two reference designs [2] and [4].…”

Section: Resultsmentioning

confidence: 99%

“…The top curve is the power (expressed as the supply current) consumed for the total for a fifth-order, 3-loop, 2-2-1 architecture, with 5 b in the first loop and 3 bits in the other two loops. It is operated at an OSR of 16 times, with a signal bandwidth of 2 MHz, as in [4]. It is worth noting the 25% reduction in current consumption by the optimization of and the fact that the minimum current of 14 mA, is well related to the reported consumption of 36 mA if folded-cascode amplifiers are used [2].…”

Section: Power Estimationmentioning

confidence: 99%

“…The state-of-the-art solution reported so far [4] is among them, (2-2-1, 5-3-3) on the axis with an FOM of 101. During the initial optimization stages, only 3 b were needed in the first loop, but yield optimization reached the 5-b solution reported in [4], the increase being needed to accommodate capacitor/ capacitor mismatch effects.…”

Section: B Delta-sigma Adc For Xdsl Applicationsmentioning

confidence: 99%

“…A MONG the many architectures of analog-to-digital converters (ADCs), designs are used in a large class of applications ranging from low-frequency [1] and audio [2] to down-converted intermediate-frequency [3] and digital video [4]. Their property to trade speed for accuracy makes them more attractive in the context of present CMOS technology evolution [5].…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Systematic Design Exploration of Delta-Sigma ADCs

Bajdechi

Gielen

Huijsing

2004

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

Abstract-An algorithm for architecture-level exploration of the 16 A/D converter (ADC) design space is presented. Starting from the desired specification, the algorithm finds an optimal solution by exhaustively exploring both single-loop and cascaded architectures, with a single-bit or multibit quantizer, for a range of oversampling ratios. A fast filter-level step evaluates the performance of all loop-filter topologies and passes the accepted solutions to the architecture-level optimization step which maps the filters on feasible architectures and evaluates their performance. The power consumption of each accepted architecture is estimated and the best top-ten solutions in terms of the ratio of peak signal-to-noise+distortion ratio versus power consumption are further optimized for yield. Experimental results for two different design targets are presented. They show that previously published solutions are among the best architectures for a given target but that better solutions can be designed as well.Index Terms-Analog-to-digital converter (ADC), analog-to-digital, computer-aided design (CAD), delta-sigma, design automation.

show abstract

“…The signal bandwidth is 2 MHz. A design has been reported [4] which consumes 90 mW in the analog circuits to attain 95 dB DR and 90 dB peak SNR.…”

Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Section: Power Estimationmentioning

confidence: 99%

Section: B Delta-sigma Adc For Xdsl Applicationsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Systematic Design Exploration of Delta-Sigma ADCs

Bajdechi

Gielen

Huijsing

2004

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

show abstract

Sigma Delta Converters in Wireline Communications

Wiesbauer

Hauptmann

Laaser³

2002

Analog Circuit Design

View full text Add to dashboard Cite

The paper contains a review of Sigma Delta ADC development with focus on multi-bit Sigma Delta ADCs. Both, achievements in the Sigma Delta area and driving applications are presented. Wireline communication products employ Sigma Delta ADCs extensively in voice band modems, ISDN modems and ADSL modems. Especially in the latter ones multi-bit Sigma Delta modulators are used. Design examples for ADSL modems are presented and recent advances, such as low voltage and deep sub-micron converters are discussed. An outlook on the developments of Sigma Delta ADCs for ADSL and VDSL is given, also covering some aspects of continuous time Sigma Delta ADCs.

show abstract

Delta-Sigma A/D-Converters

Gaggl¹

2013

Springer Series in Advanced Microelectronics

View full text Add to dashboard Cite

The Springer Series in Advanced Microelectronics provides systematic information on all the topics relevant for the design, processing, and manufacturing of microelectronic devices. The books, each prepared by leading researchers or engineers in their fields, cover the basic and advanced aspects of topics such as wafer processing, materials, device design, device technologies, circuit design, VLSI implementation, and subsystem technology. The series forms a bridge between physics and engineering and the volumes will appeal to practicing engineers as well as research scientists.

show abstract

A 2.5 V broadband multi-bit ΣΔ modulator with 95 dB dynamic range

Cited by 20 publications

References 3 publications

Systematic Design Exploration of Delta-Sigma ADCs

Systematic Design Exploration of Delta-Sigma ADCs

Sigma Delta Converters in Wireline Communications

Delta-Sigma A/D-Converters

Contact Info

Product

Resources

About