A 2.6-GHz I/O Buffer for DDR4 &amp; DDR5 SDRAMs in 16-nm FinFET CMOS Process

Ke, Jhih-Ying; Santos Tolentino, Lean Karlo; Lo, Cheng-Yao; Lee, Tzung-Je; Wang, Chua-Chin

doi:10.1109/apccas60141.2023.00068

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A 2.6-GHz I/O Buffer for DDR4 & DDR5 SDRAMs in 16-nm FinFET CMOS Process

Cited by 2 publications

References 12 publications

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GA-Optimized 6.0-Gbps DDR5 SDRAM I/O Buffer Design for 16-nm FinFET CMOS Process

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