A 2 × 6b 8 GS/s 17–24-GHz I/Q RF-DAC-Based Transmitter in 22-nm FDSOI CMOS

Aberg, Victor; Fager, Christian; Svensson, Lars

doi:10.1109/lmwc.2021.3089779

Cited by 4 publications

(3 citation statements)

References 12 publications

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“…The high sample rate enabled by the 22-nm CMOS technology together with the high resolution, segmented non-linear scaling, and a simple 1D polynomial DPD enable high-order 2 Highest sample rate achieving at least 64QAM. 3 2× interpolation in DAC. 4 4 aggregated 400 MHz channels.…”

Section: Discussionmentioning

confidence: 99%

“…The segment unit cells are based on the topology presented in [3]. The in-cell flip-flops relax the alignment constrains for the control signals and simplify the layout, as only a single signal (the sample clock) requires careful alignment throughout the RF-DAC core.…”

Section: B Segmented Rf-dacmentioning

confidence: 99%

“…Therefore, critical transmitter components, such as the digital-to-analog converters (DACs), with sufficient dynamic ranges and bandwidths for modern communication signals are keenly in need. In particular, CMOS implementation brings tight integration and low cost in such applications [3].…”

Section: Introductionmentioning

confidence: 99%

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An 11 GS/s 2×10b 20–26 GHz Modulator using Segmented Non-Linear RF-DACs and Non-Overlapping LO signals

Aberg

Fager

Hou

et al. 2022

2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

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We present a Cartesian I/Q modulator based on dual 10-bit RF-DACs. Non-overlapping LO signals and a segmented RF-DAC architecture with scaled bit currents contribute to good linearity and allow low-complexity DPD. Unit-cell flip-flops with a balanced clock distribution enable a high sample rate. Drive slope control for data switches reduce out-of-band emissions. Implemented in 22 nm FDSOI CMOS, the modulator operates up to 26 GHz with a maximum sample rate of 11 GS/s. The modulator is used to demonstrate transmission of a 64QAM signal at 13.2 Gb/s, a 256QAM signal at 7.33 Gb/s, and an OFDM signal comprising four aggregated 400-MHz 64QAM channels at an EVM of 6.43 %. The results demonstrate the potential of the proposed modulator architecture for realization of ultra wideband transmitters for high performance mm-wave systems.

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Section: Discussionmentioning

confidence: 99%

Section: B Segmented Rf-dacmentioning

confidence: 99%

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An 11 GS/s 2×10b 20–26 GHz Modulator using Segmented Non-Linear RF-DACs and Non-Overlapping LO signals

Aberg

Fager

Hou

et al. 2022

2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

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Cryogenic Controller for Electrostatically Controlled Quantum Dots in 22-nm Quantum SoC

Staszewski

Esmailiyan²,

Wang

et al. 2022

IEEE Open J. Solid-State Circuits Soc.

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We present a fully integrated cryogenic controller for electrostatically controlled quantum dots (QDs) implemented in a commercial 22-nm FD-SOI CMOS process and operating in a quantum regime. The QDs are realized in local well areas of transistors separated by tunnel barriers controlled by voltages applied to gate terminals. The QD arrays (QDA) are co-located with the control circuitry inside each quantum experiment cell, with a total of 28 of such cells comprising this system-on-chip (SoC). The QDA structure is controlled by small capacitive digital-to-analog converters (CDACs) and its quantum state is measured by a single-electron detector.The SoC operates at a cryogenic temperature of 3.4 K. The occupied area of each QD array is 0.7×0.4 µm 2 , while each QD occupies only 20×80 nm 2 . The low power and miniaturized area of these circuits are an important step on the way for integration of a large quantum core with millions of QDs, required for practical quantum computers. The performance and functionality of the CDAC are validated in a loop-back mode with the detector sensing the CDAC-compelled electron tunneling from the quantum point contact (QPC) node into the quantum structure. Position of the injected charge inside the QD array is intended to be controlled through the CDAC codes and programmable pulse width. Quantum effects are shown by an experimental characterization of charge injection and quantization into the QD array consisting of three coupled QDs. The charge can be transferred to a QD and sensed at the QPC, and this process is controlled by the relevant voltages and CDACs.Index Terms-Capacitive DAC (CDAC), charge qubits, cryo-CMOS, fully depleted silicon-on-insulator (FD-SOI), imposer, positionbased qubits, quantum computer (QC), quantum dot (QD), single-electron detector, single-electron injector. I. INTRODUCTIONQ UANTUM computing is a new paradigm that utilizes the fundamental principles of quantum mechanics, such as superposition, interference and entanglement [1], [2]. The range of complex problems from mathematics, chemistry and material science that could be solved with quantum computing is far beyond the reach of today's most powerful supercomputers. The potential is thus immense. Quantum bits (qubits), basic units of quantum information, operate at a molecular/atomic level. They are extremely fragile and difficult to manipulate and read out. Some quantum computer technologies, such as based on trapped ions and photons, do not require the equipment to be cryogenically cooled [3], [4], but the majority of qubits must operate under extremely low Manuscript received

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A 28 GHz RF-DAC With Analog LO Leakage Cancellation

Yoo

Hong

2022

IEEE Trans. Circuits Syst. II

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A 2 × 6b 8 GS/s 17–24-GHz I/Q RF-DAC-Based Transmitter in 22-nm FDSOI CMOS

Cited by 4 publications

References 12 publications

An 11 GS/s 2×10b 20–26 GHz Modulator using Segmented Non-Linear RF-DACs and Non-Overlapping LO signals

An 11 GS/s 2×10b 20–26 GHz Modulator using Segmented Non-Linear RF-DACs and Non-Overlapping LO signals

Cryogenic Controller for Electrostatically Controlled Quantum Dots in 22-nm Quantum SoC

A 28 GHz RF-DAC With Analog LO Leakage Cancellation

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