A 2-GS/s 3-bit /spl Delta//spl Sigma/-modulated DAC with tunable bandpass mismatch shaping

Kaplan, T.; Jensen, J.F.; Fields, C.H.; Chang, Mau-Chung Frank

doi:10.1109/jssc.2005.843708

Cited by 17 publications

(5 citation statements)

References 12 publications

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“…The only differences between (25) and (26) and the corresponding results for the discrete-time case, i.e., (2) and (21), are that the constant coefficients α, β, and α i in (2) and (21) are replaced by corresponding time pulses in (25) and (26). Consequently, all of the results described previously for the discrete-time case hold for the continuous-time case too.…”

Section: Extension To Continuous-time Dacsmentioning

confidence: 91%

Why Dynamic-Element-Matching DACs Work

Galton

2010

IEEE Trans. Circuits Syst. II

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This jump-start tutorial brief explains the principle that underlies all of the published mismatch-scrambling and mismatch-shaping dynamic-element-matching (DEM) digital-toanalog converters (DACs). It explains the apparent paradox of how an all-digital algorithm can cause analog component mismatches to introduce spectrally shaped noise instead of nonlinear distortion, even though the algorithm has no knowledge of the actual mismatches. The concept is first explained in the context of a discrete-time three-level DEM DAC. The results are then generalized to an arbitrary number of levels, to segmented DEM DACs, and to continuous-time DEM DACs.Index Terms-Digital-to-analog converter (DAC), dynamic element matching (DEM), mismatch scrambling, mismatch shaping.

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Section: Extension To Continuous-time Dacsmentioning

confidence: 91%

Why Dynamic-Element-Matching DACs Work

Galton

2010

IEEE Trans. Circuits Syst. II

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“…The results derived above can be generalized to the continuous-time domain. It is sufficient to modify (20) to…”

Section: B Correction Of Dac Nonlinearitiesmentioning

confidence: 99%

RX-Band Noise Reduction in All-Digital Transmitters With Configurable Spectral Shaping of Quantization and Mismatch Errors

Roverato¹,

Kosunen²,

Lemberg³

et al. 2014

IEEE Trans. Circuits Syst. I

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This paper describes the first purely digital approach to reduce the receive band noise in digitally-intensive RF transmitters. The proposed solution applies bandpass deltasigma modulation and dynamic element matching (DEM) to the receive band (RX-band) instead of the transmit band. This enables selective attenuation of the noise originating from amplitude quantization and static mismatches of the digitalto-analog converter (DAC), which would otherwise reach the transmitter output almost unattenuated. A highly configurable 4 th-order noise transfer function is designed to achieve optimum attenuation in the programmable RX-band, while ensuring negligible degradation of the transmitted signal quality as well as stable operation of the tree structure DEM encoder. A general validation of DEM, independent from the duration of the DAC impulse response, is also presented. The proposed solution is verified through system-level simulations with LTE signals. In the presence of typical amplitude and timing mismatches, the RXband noise can be reduced below-160 dBc/Hz without filtering after the DAC, thus potentially enabling SAW-less operation of all-digital transmitters.

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“…The utilization of digital ∆Σ is not limited to digital-to-analog conversion only. It is also used in analog-to-digital conversion [35][36][37][38], in phase-locked loops [39][40][41][42][43][44][45][46][47][48][49], and as a source to generate dithering signals [50][51][52][53][54][55][56], to segment the DAC further [57,58] and in multiple-input, multiple-output transceivers [59], etc. All of the above signal processing blocks are used for narrow-, wideand ultra-wide-band applications like digital audio [60][61][62], handsets [63][64][65], biomedical [66,67], TV [68][69][70], digital radio tuners [71,72] and wireless infrastructures [73][74][75].…”

Section: Introductionmentioning

confidence: 99%

Complexity and Power Reduction in Digital Delta-Sigma Modulators

Afzal

2015

Linköping Studies in Science and Technology. Dissertations

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Papers A and C are reprinted with permission from IEEE.Cover figure is an illustration of the digital cascaded error-feedback modulator.Printed by LiU-Tryck, Linköping, Sweden 2014 To my parents and teachers AbstractA number of state-of-the-art low power consuming digital delta-sigma modulator (∆Σ) architectures for digital-to-analog converters (DAC) are presented in this thesis. In an oversampling ∆Σ DAC, the primary job of the modulator is to reduce the word length of the digital control signal to the DAC and spectrally shape the resulting quantization noise. Among the ∆Σ topologies, error-feedback modulators (EFM) are well suited for so called digital to digital modulation In order to meet the demands, various modifications to the conventional EFM architectures have been proposed. It is observed that if the internal and external digital signals of the EFM are not properly scaled then not only the design itself but also the signal processing blocks placed after it, may be over designed. In order to avoid the possible wastage of resources, a number of scaling criteria are derived. In this regard, the total number of signal levels of the EFM output is expressed in terms of the input scale, the order of modulation and the type of the loop filter.Further on, it is described that the architectural properties of a unit elementbased DAC allow us to move some of the digital processing of the EFM to the analog domain with no additional hardware cost. In order to exploit the architectural properties, digital circuitry of an arbitrary-ordered EFM is split into two parts: one producing the modulated output and another producing the filtered quantization noise. The part producing the modulated output is removed after representing the EFM output with a set of encoded signals. For both the conventional and the proposed EFM architectures, the DAC structure remains unchanged. Thus, savings are obtained since the bits to be converted are not accumulated in the digital domain but instead fed directly to the DAC.A strategy to reduce the hardware of conventional EFMs has been devised recently that uses multiple cascaded EFM units. We applied the similar approach but used several cascaded modified EFM units. The compatibility issues among the units (since the output of each proposed EFM is represented by the set of encoded signals) are resolved by a number of architectural modifications. The digital processing is distributed among each unit by splitting the primary input bus. It is shown that instead of cascading the EFM units, it is enough to cascade their loop filters only. This leads not only to area reduction but also to the reduction of power consumption and critical path.All of the designs are subjected to rigorous analysis and are described mathev vi Abstract matically. The estimates of area and power consumption are obtained after synthesizing the designs in a 65 nm standard cell library provided by the foundry. Populärvetenskaplig sammanfattning vii viiiPopulärvetenskaplig sammanfattning I denna avhandling presenteras e...

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A 2-GS/s 3-bit /spl Delta//spl Sigma/-modulated DAC with tunable bandpass mismatch shaping

Cited by 17 publications

References 12 publications

Why Dynamic-Element-Matching DACs Work

Why Dynamic-Element-Matching DACs Work

RX-Band Noise Reduction in All-Digital Transmitters With Configurable Spectral Shaping of Quantization and Mismatch Errors

Complexity and Power Reduction in Digital Delta-Sigma Modulators

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