A 200MS/s, 11 bit SAR-assisted pipeline ADC with bias-enhanced ring amplifier

Chen, Yongzhen; Wang, Jingjing; Hu, Hang; Ye, Fan; Ren, Junyan

doi:10.1109/iscas.2017.8050244

Cited by 11 publications

(7 citation statements)

References 2 publications

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“…In addition, the signal can be rapidly amplified through slew-based charging rather than the RC-based charging used in conventional op-amps, and power consumption is very low. The values of the parameters listed in Table 1 confirm that, using a ring amplifier, a pipeline structure can be advantageous in terms of power and speed without additional circuits [10][11][12][13]. However, even if a ring amplifier is used, if a pipeline-SAR ADC tries to implement even higher resolution, each stage requires further fine quantization, and the comparator design can be an issue.…”

Section: Introductionmentioning

confidence: 92%

“…An op-amp/operational trans-conductance amplifier (OTA) with a high open-loop gain is used in most pipelined structures because of its tolerance to filter mismatch. Among the various structures available, a gain-boosting, cascode-type op-amp is often used conventionally, as shown in Figure 4a [7,13,22,23]. However, it accounts for most of…”

Section: Ring Amplifiermentioning

confidence: 99%

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A Pipelined Noise-Shaping SAR ADC Using Ring Amplifier

Lee

Kim

et al. 2021

Electronics

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In this study, a pipelined noise-shaping successive-approximation register analog-to-digital converter (PLNS-SAR ADC) structure was proposed to achieve high resolution and to be free from comparator design requirements. The inter-stage amplifier and integrator of the PLNS-SAR ADC were implemented through a ring amplifier with high gain and speed. The ring amplifier was designed to improve power efficiency and be tolerant to process–voltage–temperature (PVT) variation, and uses a single loop common-mode feedback (CMFB) circuit. By processing residual signals with a single ring amplifier, power efficiency can be maximized, and a low-power system with 30% lower power consumption than that of a conventional PLNS-SAR ADC is implemented. With a high-gain ring amplifier, noise leakage is greatly suppressed, and a structure can be implemented that is tolerant of mismatches between the analog loop and digital correction filters. The measured signal to noise distortion ratio (SNDR) is 70 dB for a 5.15 MHz bandwidth (BW) at a 72 MS/s sampling rate (Fs) with an oversampling ratio (OSR) of 7, and the power consumption is 2.4 mW. The (= SNDR + BW/Power) is 163.5 dB. The proposed structure in this study can achieve high resolution and wide BW with good power efficiency, without a filter calibration process, through the use of a ring amplifier in the PLNS-SAR ADC.

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Section: Introductionmentioning

confidence: 92%

Section: Ring Amplifiermentioning

confidence: 99%

A Pipelined Noise-Shaping SAR ADC Using Ring Amplifier

Lee

Kim

et al. 2021

Electronics

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show abstract

“…More importantly, ringamps are more suitable for fine CMOS processes and have application scenarios in various types of ADCs due to the versatility of their structures. In the last decade, many ringamp-based ADC works [24,[29][30][31][32][33][34][35][36][37][38][39] have appeared. Essentially, there are two different directions of the application, one for high resolution (signal-to-noise-and-distortion-ratio (SNDR) ≥ 70 dB) and the other for high speed (sampling rate fs ≥ 500 MHz), such as the dual-deadzone RAMP-based two-step SAR ADC [34], which achieves the highest SNDR for a ringampbased high-resolution ADC, while [33] used a dead zone degeneration technique to realize the fastest sampling rate (fs = 1 GHz) for single-channel implementation.…”

Section: Ring Amplifier Reviewmentioning

confidence: 99%

“…The self-biased ringamp [30] is replaced by a resistor R DZ inserted in the second stage to separate the signal without additional bias capacitors, enabling the transition of the ringamp from oscillation to amplification, due to the nature of the ringamp, which originates from a ring oscillator. The bias-enhanced ringamp is originally proposed in [31] by inserting a resistor R BE in the first stage and cross-coupling the top and bottom nodes of the resistors to the second stage. Due to the increase in the overdrive voltage of the second stage transistors, bias-enhanced ringamp can achieve larger bandwidth.…”

Section: Ring Amplifier Reviewmentioning

confidence: 99%

A 2.5-GS/s Four-Way-Interleaved Ringamp-Based Pipelined-SAR ADC with Digital Background Calibration in 28-nm CMOS

et al. 2021

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A 2.5-GS/s 12-bit four-way time-interleaved pipelined-SAR ADC is presented in 28-nm CMOS. A bias-enhanced ring amplifier is utilized as the residue amplifier to achieve high bandwidth and excellent power efficiency compared with a traditional operational amplifier. A high linearity front-end is proposed to alleviate the non-linearity of the diode for ESD protection in the input PAD. The embedded input buffer can suppress the kickback noise at high input frequencies. A blind background calibration based on digital-mixing is used to correct the mismatches between channels. Additionally, an optional neural network calibration is also provided. The prototype ADC achieves a low-frequency SNDR/SFDR of 51.0/68.0 dB, translating a competitive FoMw of 0.48 pJ/conv.-step at 250 MHz input running at 2.5 GS/s.

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“…In [2], a dynamic dead-zone implemented with a resistor was presented, which was used in [4] to create a fully differential RA. In [5], a second-stage bias-enhanced RA showed improved performance, and in [6], the bias-enhancing technique was used in conjunction with a degenerated deadzone to improve the linearity and bandwidth of the RA.…”

Section: Introductionmentioning

confidence: 99%

34.3 fJ/conv.-step 8-MHz Bandwidth Fourth-Order Pseudo-Differential Ring-Amplifier-Based Continuous-Time Delta–Sigma ADC in 65 nm

Muntal

Jørgensen

2018

IEEE Solid-State Circuits Lett.

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A 200MS/s, 11 bit SAR-assisted pipeline ADC with bias-enhanced ring amplifier

Cited by 11 publications

References 2 publications

A Pipelined Noise-Shaping SAR ADC Using Ring Amplifier

A Pipelined Noise-Shaping SAR ADC Using Ring Amplifier

A 2.5-GS/s Four-Way-Interleaved Ringamp-Based Pipelined-SAR ADC with Digital Background Calibration in 28-nm CMOS

34.3 fJ/conv.-step 8-MHz Bandwidth Fourth-Order Pseudo-Differential Ring-Amplifier-Based Continuous-Time Delta–Sigma ADC in 65 nm

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