A 200MS/s, 8-bit Time-based Analog to Digital Converter (TADC) in 65nm CMOS technology

Abdel‐Kader, Mahmoud H.; Ali, Ahmed; Abdelaziz, Ahmed; Ismail, M.; Refky, Mohamed; Ismail, Yehea; Mostafa, Hassan

doi:10.1109/jec-ecc.2016.7518960

Cited by 2 publications

(3 citation statements)

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“…Advances in solutions that address digital formation have led to the development of complementary metal-oxide-semiconductor (CMOS) technology sampling prototypes [7][8][9][10][11][12]. Emerging attempts to address optimization of dynamic range resolution have led to the development of a modulo analog-to-digital converter [13].…”

Section: Literature Reviewmentioning

confidence: 99%

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Odd/Even Order Sampling Soft-Core Architecture Towards Mixed Signals Fourth Industrial Revolution (4IR) Applications

2019

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Digitization is at the center of fourth industrial revolution (4IR) with previously analog systems being digitized through an analog-to-digital converter. In addition, 4IR applications such as fifth generation (5G) Cellular Networks Technology and Cognitive Electronic Warfare (EW) at some point interface digitally through an analog-to-digital converter. Efficient use of digital resources such as memory, largely depends on the signal sampling design of analog-to-digital converters. Existing even order sampling has been found to perform better than traditional sampling techniques. Research on the efficiency of a digital interface with a 4IR platform is still in its infancy. This paper presents a performance study of three sampling techniques: the proposed new and novel odd/even order sampling architecture, existing Mod-∆, and traditional 1st order delta-sigma, to address this. Step-size signal-to-noise (SNR), dynamic range, and sampling frequency are also studied. It was found that the proposed new and novel odd/even order sampling achieved an SNR performance of 6 dB in comparison to 18 dB for Mod-∆. Sampling frequency findings indicated that the proposed new and novel odd/even order sampling achieved a sampling frequency of 2 kHz in comparison to 8 kHz from a traditional 1st order sigma-delta. Dynamic range findings indicated that the proposed odd/even order sampling has achieved a dynamic range of 1.088 volts/ms in comparison to 1.185 volts/ms from a traditional 1st order sigma-delta. Findings have indicated that the proposed odd/even order sampling has superior SNR and sampling frequency performances, while the dynamic range is reduced by 8%.

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Section: Literature Reviewmentioning

confidence: 99%

“…The Odd order I/Q demodulator presented in reference [2] does not clearly derive the odd 3rd order sampling characterization equation that it presents. Equations (6) and (7) in this paper initiate the derivation for the proposed odd/even order sampling algorithm:…”

Section: Odd Order Samplingmentioning

confidence: 99%

Odd/Even Order Sampling Soft-Core Architecture Towards Mixed Signals Fourth Industrial Revolution (4IR) Applications

2019

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“…From the table 6-6, it can be seen what the various input ranges are in comparison to the supply voltage. The current starving approach used in[96] uses both PMOS and NMOS current starving transistors to increase the range up to twofold of what was presented in…”

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confidence: 99%

Design of digital-intensive time-mode data converters based on delay correction utilising a time-to-digital converter

Kong¹

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A 200MS/s, 8-bit Time-based Analog to Digital Converter (TADC) in 65nm CMOS technology

Cited by 2 publications

References 2 publications

Odd/Even Order Sampling Soft-Core Architecture Towards Mixed Signals Fourth Industrial Revolution (4IR) Applications

Odd/Even Order Sampling Soft-Core Architecture Towards Mixed Signals Fourth Industrial Revolution (4IR) Applications

Design of digital-intensive time-mode data converters based on delay correction utilising a time-to-digital converter

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