A 237–263 GHz CMOS Frequency Doubler with 0.9 dBm Output Power and 2.87 % Power Efficiency Based on Harmonic Matched $G_{\max}$-Core

Moon, Byeong-Taek; Yun, Byeonghun; Lee, Sang‐Gug

doi:10.1109/ims37962.2022.9865611

Cited by 4 publications

(1 citation statement)

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“…In this work, we propose a frequency doubler with a gain boosting technique to improve the harmonic output power while ensuring good power efficiency without requiring additional amplifying stages [15]. Then, by adopting the dual-band matching method, the second harmonic signal is effectively extracted and delivered to the load while maintaining the high fundamental gain.…”

Section: Introductionmentioning

confidence: 99%

Analysis and Design of Power-Efficient H-Band CMOS Frequency Doubler Employing Gain Boosting and Harmonic Enhancing Techniques

et al. 2023

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This article presents a power-efficient frequency doubler employing gain boosting and harmonic-enhancing techniques. With a single transistor only, the gain boosting technique can reach the maximum achievable gain (Gmax) by adding embedded passive components, thereby obtaining high voltage swings. Then, the transistor's nonlinearity is essential, which is maximized by the harmonic transition scheme of the transistor operation along with high voltage swings. In addition, a harmonic reflector and a harmonic leakage canceller are employed for the second harmonic enhancement. The harmonic reflector prevents unwanted harmonic mixing by minimizing the incoming second harmonic current fed back to the input. The harmonic leakage canceller suppresses the leakage loss of the second harmonic current present at the output. Furthermore, thanks to a proposed dual-band output matching network, the output impedance is conjugately matched to achieve the Gmax at the fundamental frequency while it is matched to extract the second harmonic output power simultaneously. To verify the proposed techniques, the prototype was designed as a single-stage circuit that does not require additional amplifying stages, which led to higher power efficiency and lower chip area. Implemented in a 65-nm CMOS process, the measurement results show a saturated output power of 0.9 dBm and 3-dB bandwidth of 26 GHz (237−263 GHz), respectively, while requiring a chip area of 0.071 mm 2 . Total power efficiency, including the effect of injected signal power, is 2.87 % while consuming only 37 mW dc power.

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Section: Introductionmentioning

confidence: 99%

Analysis and Design of Power-Efficient H-Band CMOS Frequency Doubler Employing Gain Boosting and Harmonic Enhancing Techniques

et al. 2023

Self Cite

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24.2 A 264-to-287GHz, −2.5dBm Output Power, and −92dBc/Hz 1MHz-Phase-Noise CMOS Signal Source Adopting a 75fs_rms Jitter D-Band Cascaded Sub-Sampling PLL

Moon

Lee

Choi

2023

2023 IEEE International Solid- State Circuits Conference (ISSCC)

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A Compact 24.5–32.6 GHz CMOS Frequency Doubler Based on Coupled Inductor

Ding,

Shen,

Lin

et al. 2024

IEEE Trans. Circuits Syst. II

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A 237–263 GHz CMOS Frequency Doubler with 0.9 dBm Output Power and 2.87 % Power Efficiency Based on Harmonic Matched $G_{\max}$-Core

Cited by 4 publications

References 8 publications

Analysis and Design of Power-Efficient H-Band CMOS Frequency Doubler Employing Gain Boosting and Harmonic Enhancing Techniques

Analysis and Design of Power-Efficient H-Band CMOS Frequency Doubler Employing Gain Boosting and Harmonic Enhancing Techniques

24.2 A 264-to-287GHz, −2.5dBm Output Power, and −92dBc/Hz 1MHz-Phase-Noise CMOS Signal Source Adopting a 75fs_rms Jitter D-Band Cascaded Sub-Sampling PLL

A Compact 24.5–32.6 GHz CMOS Frequency Doubler Based on Coupled Inductor

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A 237–263 GHz CMOS Frequency Doubler with 0.9 dBm Output Power and 2.87 % Power Efficiency Based on Harmonic Matched $G_{\max}$-Core

Cited by 4 publications

References 8 publications

Analysis and Design of Power-Efficient H-Band CMOS Frequency Doubler Employing Gain Boosting and Harmonic Enhancing Techniques

Analysis and Design of Power-Efficient H-Band CMOS Frequency Doubler Employing Gain Boosting and Harmonic Enhancing Techniques

24.2 A 264-to-287GHz, −2.5dBm Output Power, and −92dBc/Hz 1MHz-Phase-Noise CMOS Signal Source Adopting a 75fsrms Jitter D-Band Cascaded Sub-Sampling PLL

A Compact 24.5–32.6 GHz CMOS Frequency Doubler Based on Coupled Inductor

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Product

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24.2 A 264-to-287GHz, −2.5dBm Output Power, and −92dBc/Hz 1MHz-Phase-Noise CMOS Signal Source Adopting a 75fs_rms Jitter D-Band Cascaded Sub-Sampling PLL