A 240-mW 2.1-GS/s 52-dB SNDR Pipeline ADC Using MDAC Equalization

Wu, Jiangfeng; Chen, Chunying; Li, Tianwei; He, Liang; Liu, Wenbo; Shih, Wei-Ta; Tsai, Shauhyuarn Sean; Chen, Binning; Huang, Chun‐Sheng; Hung, Bryan Juo-Jung; Hung, Hing; Jaffe, Steven M.; Tan, Loke Kun; Vu, Hung

doi:10.1109/jssc.2013.2259013

Cited by 27 publications

(9 citation statements)

References 26 publications

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“…A foreground calibration algorithm proposed by [14] is employed to correct the mismatch of capacitors for more precise gain. Telescopic cascode op amps with gain boosting on both the NMOS side and the PMOS side are also employed to realize large open-loop DC gain and high gain bandwidth which can further address the nonlinearity and noise [15].…”

Section: Adc Core Designmentioning

confidence: 99%

A 14 bit 500 MS/s SHA-less pipelined ADC with a highly linear input buffer and power-efficient supply voltage domain arrangement in 40 nm CMOS

Chen¹,

Shen³

et al. 2019

IEICE Electron. Express

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In this paper, a 14 bit 500 MS/s SHA-less pipelined Analog-to-Digital Converter (ADC) realized in 40 nm CMOS technology is presented. A 2.5 V powered buffer that exhibits a comprehensive bootstrap architecture is proposed to achieve the trade-off between linearity and power consumption. Besides, the high-voltage-thin-oxide-device design is incorporated to further improve the linearity. In the meantime, an improved supply voltage domain arrangement is proposed to achieve a single power design and improve structural power efficiency. The measured Signal-to-Noise-and-Distortion-Ratio (SNDR) and Spurious-Free-Dynamic-Range (SFDR) are 71 dB and 79 dBc at 120.2 MHz input signal under 500 MS/s. The ADC occupies an active area of 0.4 mm 2 and consumes a total power of 300 mW.

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Section: Adc Core Designmentioning

confidence: 99%

A 14 bit 500 MS/s SHA-less pipelined ADC with a highly linear input buffer and power-efficient supply voltage domain arrangement in 40 nm CMOS

Chen¹,

Shen³

et al. 2019

IEICE Electron. Express

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“…Indirect conversion TDCs can be divided into the ramp TDCs [11], and the multi-slope pulse stretching TDCs [12], [13]. There are also converters that take advantage of the interpolation technique for conversion which is implemented based on multi-slope pulse stretching methods [9], [14], [15]. The interpolation circuits are usually united with the counterbased TDCs to increase the input range to infinity [9].…”

Section: Introductionmentioning

confidence: 99%

A Novel Cyclic Time to Digital Converter Based on Triple-Slope Interpolation and Time Amplification

Farshidi¹,

Rezvanyvardom²

2015

RADIOENGINEERING

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This paper investigates a novel cyclic time-todigital converter (TDC) which employs triple-slope analog interpolation and time amplification techniques for digitizing the time interval between the rising edges of two input signals (Start and Stop). The proposed converter will be a 9-bit cyclic time-to-digital converter that does not use delay lines in its structure. Therefore, it has a low sensitivity to temperature, power supply and process (PVT) variations. The other advantages of the proposed converter are low circuit complexity, and high accuracy compared with the time-to-digital converters that have previously been proposed. This converter also improves the time resolution and the dynamic range. In the same resolution, linear range and dynamic range, the proposed cyclic TDC reduces the number of circuit elements compared with the converters that have a similar circuit structure. Thus, the converter reduces the chip area, the power consumption and the figure of merit (FoM). In this converter, the integral nonlinearity (INL) and differential nonlinearity (DNL) errors are reduced. In order to evaluate the idea, the proposed time-to-digital converter is designed in TSMC 45 nm CMOS technology and simulated. Comparison of the theoretical and simulation results confirms the benefits of the proposed TDC.

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“…Another consideration for the MDAC is the need for sufficient time to settle to the required accuracy (settling error <½LSB). In the case of an 11bit ADC, the MDAC requires >7.6τ [4,61], where τ is the settling time constant. In view of the timeconsuming operation [23] and timing overheads [7] of conventional pipeline stages, the settling time available for the MDAC is acutely limited.…”

Section: Discussionmentioning

confidence: 99%

“…In view of these stringent requirements, it is well recognized [2][3][4] that the design and realization of such ADCs are challenging, particularly the high power-efficiency attribute at GS/s and multi-GS/s conversion rate. To appreciate these challenges, rate exceeds approximately 300MS/s.…”

Section: List Of Tablesmentioning

confidence: 99%

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Design and monolithic realization of high-speed high-resolution analog-to-digital converters

Liu¹

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This PhD program pertains to the design and monolithic realization of high-speed high-resolution Analog-to-Digital Converters (ADCs), particularly pipeline-based and Successive Approximation Register (SAR)-based architectures, for next-generation telecommunication systems. The primary objectives are to increase the speed and the resolution of these ADCs by means of innovative techniques/approaches, yet with minimal hardware and power overheads, and accommodating the ever-finer technology nodes. Interestingly, although the design art of pipeline and SAR ADCs are well established, several aspects of state-of-the-art designs and realizations remain inadequate. These inadequacies include the Multiplying Digital-to-Analog Converter (MDAC) in pipeline-based ADCs constraining the resolution, and the conversion algorithm of SAR-based ADCs limiting the speed. For the pipeline-based ADC, we propose, design, and monolithically realize a novel time-interleaved (×2) 11bit 1GS/s SAR-assisted MDAC-free pipeline architecture. At the system level, we propose to employ a front-end sample-and-hold to mitigate the problematic timing mismatch between the two time-interleaved channel ADCs. We further propose to predetermine the MSB (Most Significant Bit) outside the channel ADCs to substantially simplify the requirement of the channel ADCs. At the block level, we propose an innovative MDAC-free pipeline architecture for the channel ADCs where the MDAC is absent-to the best of our knowledge, this is the first-ever reported MDAC-free pipeline ADC architecture. The significance of the MDAC-free feature is particularly valuable to the pipeline ADC design as the well-reported critical issues arising from the MDACs are largely circumvented. Particularly, this leads to higher speed and higher accuracy, yet with potentially reduced design complexity. Further, this

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A 240-mW 2.1-GS/s 52-dB SNDR Pipeline ADC Using MDAC Equalization

Cited by 27 publications

References 26 publications

A 14 bit 500 MS/s SHA-less pipelined ADC with a highly linear input buffer and power-efficient supply voltage domain arrangement in 40 nm CMOS

A 14 bit 500 MS/s SHA-less pipelined ADC with a highly linear input buffer and power-efficient supply voltage domain arrangement in 40 nm CMOS

A Novel Cyclic Time to Digital Converter Based on Triple-Slope Interpolation and Time Amplification

Design and monolithic realization of high-speed high-resolution analog-to-digital converters

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