A 250 mV, 352 $\mu$W GPS Receiver RF Front-End in 130 nm CMOS

Heiberg, Adam C.; Brown, Thomas W.; Fiez, T.S.; Mayaram, K.

doi:10.1109/jssc.2011.2109470

Cited by 58 publications

(24 citation statements)

References 23 publications

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“…The result shows that S 11 of the LNA-Mixer is less than −18 dB over a frequency range of 1.5∼1. 6 GHz. An appropriate input matching network guarantees well performance of S 11 and NF.…”

Section: Resultsmentioning

confidence: 99%

“…Among the techniques proposed to reduce the power consumption of LNAs, current-reuse is an effective method worth adopting. Many studies mentioned in references focus on power consumption reducing and noise improvement, such as current-reuse [1,2,3,4], gm-boosting [5] and using sub-threshold MOSFETs techniques [6]. However, the LNA and the mixer are two separated circuits, thus there is still room for improvement on power consumption and the chip area.…”

Section: Introductionmentioning

confidence: 99%

“…As to mixers, the noise performance of the active mixer is better than the existing passive mixer, but in price of more power consumption and chip area [3,6,7,8,9]. Hence, passive mixer is always a valuable choice when considering about linearity, power consumption and chip size.…”

Section: Introductionmentioning

confidence: 99%

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A compact low power current-mode LNA-Mixer for RF receiver

Zhao

Liao²

2017

IEICE Electron. Express

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A compact low-power current-mode LNA-Mixer with currentreuse architecture used for RF receiving applications is presented. The current-mode mixer reuses the current of the LNA directly to get further minimization on power consumption, complexity and area, making the LNA and the mixer acting as a single circuit. The NF of the LNA is improved by using a capacitive cross-couple structure cooperating with noise suppression inductors. And the single-ended voltage signal is converted to differential current signal so as to improve the common-mode noise rejection ratio. Different from voltage-mode passive mixer, the higher gain compensation and low noise are obtained by switching current mirror method combined with source degradation noise suppression technology. The proposed LNAMixer implemented in 0.18 µm CMOS process can obtain a NF of 3.1 dB, a IP 1-dB of −31.6 dBm, a small core size of 0.39 mm 2 and a power consumption of 8 mW.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A compact low power current-mode LNA-Mixer for RF receiver

Zhao

Liao²

2017

IEICE Electron. Express

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“…Especially [9] has a much higher linearity at the cost of a high power consumption, which makes the receiver better suited for high performance applications. Additionally, it is clear that the low supply voltage of 0.25V used in [16] leads to a low 1dB compression point and low IIP3. The increased noise figure of the reported receiver can be explained by the absence of the LNA and the very low power consumption of the VCO.…”

Section: Comparison With Literaturementioning

confidence: 99%

“…Compared to the reported FSK receivers, the WURxV2.1 has a low power consumption, especially taken into account that [12,13,16] do not have frequency calibration or an on-chip demodulator. Direct comparison in power consumption is difficult since also other parameters are different.…”

Section: Comparison With Literaturementioning

confidence: 99%

Wake-up Receiver Based Ultra-Low-Power WBAN

Lont¹

2014

Analog Circuits and Signal Processing

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Modeling of high‐frequency noise of silicon CMOS transistors for RFIC design

Antonopoulos

Bucher

Papathanasiou

et al. 2014

Int J Numerical Modelling

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SUMMARYThis work presents high-frequency noise measurements and compact modeling for a 90-nm silicon complementary metal-oxide-semiconductor (CMOS) technology in terms of radio frequency (RF) figures of merit (FoMs). Minimum noise figure (NF min ), equivalent noise resistance (R n ), optimum source reflection coefficient (Γ opt ), thermal noise excess factor and a recently introduced FoM for common-source low-noise amplifier (LNA) design are presented from a circuit design perspective. For this purpose, the behavior of the above mentioned RF FoMs is investigated over the level of channel inversion, providing insight from a circuit design point of view. The EKV3 MOSFET advanced compact model has been used in Spectre simulator, and results are validated over a large range of frequencies, channel lengths and bias points, for both N-type and P-type MOS devices. Optimum performance is shown to be shifted from higher to lower levels of inversion in moderate inversion, when scaling from 240 nm down to 100 nm. This is of great significance considering that the demand for low-power RF circuits becomes more and more imperative, as planar silicon CMOS technology is scaled to the deca-nanometer regime.

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A 250 mV, 352 $\mu$W GPS Receiver RF Front-End in 130 nm CMOS

Cited by 58 publications

References 23 publications

A compact low power current-mode LNA-Mixer for RF receiver

A compact low power current-mode LNA-Mixer for RF receiver

Wake-up Receiver Based Ultra-Low-Power WBAN

Modeling of high‐frequency noise of silicon CMOS transistors for RFIC design

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