A −254.1-dB FoM 2.4-GHz Subsampling PLL With a −76-dBc Reference Spur by Employing a Varactor-Based Cancellation Technique

Lee, Dhon-Gue; Nikoofard, Ali; Mercier, Patrick P.

doi:10.1109/lssc.2020.3007687

Cited by 5 publications

(4 citation statements)

References 5 publications

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“…In the high frequency transceiver, the PLL is the key design element and plays an important role in the overall receiver performance [2]. There has been a significant rise in ongoing research of millimeter wave PLLs that use less power and have more convenient architecture, thereby bringing the amount of insignificant content down to conventional standards [3,4]. Several kinds of PLLs are not appropriate for usage in the nodes that include a WSN.…”

Section: Introductionmentioning

confidence: 99%

A Novel 65 nm Active-Inductor-Based VCO with Improved Q-Factor for 24 GHz Automotive Radar Applications

Behera

Siddique

Delwar

et al. 2022

Sensors

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The inductor was primarily developed on a low-voltage CMOS tunable active inductor (CTAI) for radar applications. Technically, the factors to be considered for VCO design are power consumption, low silicon area, high frequency with reasonable phase noise, an immense quality (Q) factor, and a large frequency tuning range (FTR). We used CMOS tunable active inductor (TAI) topology relying on cascode methodology for 24 GHz frequency operation. The newly configured TAI adopts the additive capacitor (Cad) with the cascode approach, and in the subthreshold region, one of the transistors functions as the TAI. The study, simulations, and measurements were performed using 65nm CMOS technology. The assembled circuit yields a spectrum from 21.79 to 29.92 GHz output frequency that enables sustainable platforms for K-band and Ka-band operations. The proposed design of TAI demonstrates a maximum Q-factor of 6825, and desirable phase noise variations of −112.43 and −133.27 dBc/Hz at 1 and 10 MHz offset frequencies for the VCO, respectively. Further, it includes enhanced power consumption that varies from 12.61 to 23.12 mW and a noise figure (NF) of 3.28 dB for a 24 GHz radar application under a low supply voltage of 0.9 V.

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Section: Introductionmentioning

confidence: 99%

A Novel 65 nm Active-Inductor-Based VCO with Improved Q-Factor for 24 GHz Automotive Radar Applications

Behera

Siddique

Delwar

et al. 2022

Sensors

View full text Add to dashboard Cite

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“…Numerous research results of CPPLL have been published, such as [9][10][11][12][13][14]. In [11], a CPPLL is realized using a 65 nm Si CMOS process.…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of Charge Pump Phase-Locked Loop Frequency Source Based on GaAs pHEMT Process

Zhao

Zhang

et al. 2022

Sensors

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This paper realized a charge pump phase locked loop (CPPLL) frequency source circuit based on 0.15 μm Win GaAs pHEMT process. In this paper, an improved fully differential edge-triggered frequency discriminator (PFD) and an improved differential structure charge pump (CP) are proposed respectively. In addition, a low noise voltage-controlled oscillator (VCO) and a static 64:1 frequency divider is realized. Finally, the phase locked loop (PLL) is realized by cascading each module. Measurement results show that the output signal frequency of the proposed CPPLL is 3.584 GHz–4.021 GHz, the phase noise at the frequency offset of 1 MHz is −117.82 dBc/Hz, and the maximum output power is 4.34 dBm. The chip area is 2701 μm × 3381 μm, and the power consumption is 181 mw.

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“…Recent studies demonstrated sub-sampling PLLs (SSPLLs) where the phase error is linearly sampled and controls the voltage-controlled oscillator (VCO) frequency with no quantization noise [16][17][18][19][20]. The SSPLLs have achieved low in-band phase noise by using a sample-and-hold circuit and eliminating a divider from the PLL feedback path.…”

Section: Introductionmentioning

confidence: 99%

“…The SSPLLs have achieved low in-band phase noise by using a sample-and-hold circuit and eliminating a divider from the PLL feedback path. However, the SSPLLs alone may be a false lock to an uncertain multiple of the reference frequency due to an arbitrary phase offset, and then the SSPLL requires an additional frequency-locked loop (FLL) to avoid the false lock [18][19][20].…”

Section: Introductionmentioning

confidence: 99%

A 3-3.7GHz Time-Difference Controlled Digital Fractional-N PLL With a High-Gain Time Amplifier for IoT Applications

et al. 2022

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This paper presents analyses of jitter and reference spur of a digital PLL using a phasefrequency detector (PFD) and a time amplifier (TA). In the PFD-TA PLL, the TA amplifies a phase error between a reference clock and a divided feedback clock. The amplified pulse signals modulate the digitally controlled oscillator (DCO) frequency. The TA input-referred jitter limits the minimum PFD-TA PLL output jitter in case of the low DCO and reference clock jitter. However, the PFD-TA PLL achieves a lower output jitter than the BBPLL especially when the input noise is worsened by the poor DCO, which, indeed, is common in low-power and IoT applications for lower cost and power. The reference spur caused by the path mismatches of the proposed DCO modulation is analyzed by Fourier Series, and implementing the high-gain (>100) TA reduces the reference spur with the smaller DCO modulating signal distortion. To assist the narrow input dynamic range (<30ps) of the TA, a 7-bit phase interpolator (PI) is implemented to fractional frequency divider with a PI nonlinearity calibration. The theoretical predictions are compared with the behavioral simulations and verified in measurements where the chip is fabricated in a 40 nm CMOS process, and the PFD-TA PLL consumes 5 mW from a 1.1 V supply.INDEX TERMS Time amplifier (TA), digitally controlled oscillator (DCO), digital phase-locked loop (PLL), PLL jitter analysis, reference spur, phase interpolator (PI) nonlinearity calibration.

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A −254.1-dB FoM 2.4-GHz Subsampling PLL With a −76-dBc Reference Spur by Employing a Varactor-Based Cancellation Technique

Cited by 5 publications

References 5 publications

A Novel 65 nm Active-Inductor-Based VCO with Improved Q-Factor for 24 GHz Automotive Radar Applications

A Novel 65 nm Active-Inductor-Based VCO with Improved Q-Factor for 24 GHz Automotive Radar Applications

Design and Implementation of Charge Pump Phase-Locked Loop Frequency Source Based on GaAs pHEMT Process

A 3-3.7GHz Time-Difference Controlled Digital Fractional-N PLL With a High-Gain Time Amplifier for IoT Applications

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