A 28 GHz Linear Power Amplifier Based on CPW Matching Networks with Series-Connected DC-Blocking Capacitors

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This paper presents a low power two-stage single-end (SE) 28 GHz low-noise amplifier (LNA) in 90 nm silicon-on-insulator (SOI) CMOS technology for 5G applications. In this design, the influence of bias circuit is discussed. The 1200 Ω resistor which was adopted in bias circuit can feed DC voltage as well as keep whole circuit unconditionally stable. The gate bias points are set to 0.55 V to make the circuit low-power and temperature-stable. Measurement results illustrated that the LNA achieved a maximum small signal gain of 18.1 dB and an average 3.1 dB noise figure (NF) in operating frequency band. Measured S11 was below −10 dB between 25 GHz and 29 GHz and reverse isolation S12 was below −25 dB throughout the band. It consumed only 4 mW by proper selection of bias point with core area of 0.16 mm2 without pads. The fabricated LNA has demonstrated a gain variation of 3 dB and a NF variation of 1.9 dB from −40 °C to 125 °C with power variation of 0.8 mW. It suggests that the proposed SOI CMOS LNA can be a promising candidate for 5G applications.

Section: Introductionmentioning

confidence: 95%

A 4-mW Temperature-Stable 28 GHz LNA with Resistive Bias Circuit for 5G Applications

Xia

Huang

et al. 2020

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23.5–27.5 GHz Band Doherty Power Amplifier Integrated Circuit Using 28 nm Bulk CMOS Process Based on Dynamic Power Dividing Network

Choi,

Bin,

Hwang

et al. 2024

This paper presents a Doherty power amplifier (DPA) integrated circuit (IC) designed to have enhanced gain, efficiency, and AM-AM characteristics through a dynamic power dividing technique, which can control the power dividing ratio according to the input power. Since this multi-purpose dynamic power dividing network also provides the phase offset and impedance matching at the interstage network needed for appropriate DPA operation, the active IC area could be reduced. To verify the proposed technique and its analysis, the DPA was implemented with a 28 nm bulk CMOS process for the fifth-generation (5G) new radio (NR) millimeter-wave frequency band of 23.5–27.5 GHz. The measured results showed a gain of 20.3–21.9 dB, saturated output power of 14.0–15.2 dBm, power added efficiency (PAE) of 22.8–26.7% at the peak power, and PAE of 14.6–17.6% at the 6 dB output power back-off (OBO).

Frequency Selective Degeneration for 6–18 GHz GaAs pHEMT Broadband Power Amplifier Integrated Circuit

Yoo

et al. 2020

In this paper, a frequency selective degeneration technique using a parallel network with a resistor and capacitor is proposed for a 6–18 GHz GaAs pseudomorphic high electron mobility transistor (pHEMT) broadband power amplifier integrated circuit (PAIC). The proposed degeneration network is applied to the source of the transistor to flatten the frequency response of the transistor in conjunction with feedback and resistor biasing circuits. An almost uniform frequency response was achieved at the wide frequency band through optimizing the values of the capacitor and resistor for the degeneration circuit. Single-section matching networks for small chip sizes were adopted for the two-stage amplifier following the flat frequency characteristics of the degenerated transistor. The proposed broadband PAIC for the 6 to 18 GHz band was fabricated using a 0.15 μm GaAs pHEMT process and had a chip size of 1.03 × 0.87 mm2. The PAIC exhibited gain of 15 dB to 17.2 dB, output power of 20.5 dBm to 22.1 dBm, and linear output power of 11.9 dBm to 13.45 dBm, which satisfies the IMD3 of −30 dBc in the 6–18 GHz band. Flatness for the gain and output power was achieved as ±1.1 dB and ±0.8 dB, respectively.