A 3.1 mW Continuous-Time ΔΣ Modulator With 5-Bit Successive Approximation Quantizer for WCDMA

A low-power 2nd-order CT delta–sigma modulator with an asynchronous SAR quantizer

“…In [4], a SAR quantizer was used in a discretetime (DT) DSM for audio applications. Furthermore, two CT DSMs with SAR quantizers have been described in [6,7]. When used in a CT DSM, the SAR quantizer will introduce a loop delay, t d , as it requires several clock cycles to perform the conversion.…”

“…1 for N ¼ 4. Generation of this clock requires additional power and area and a delaylocked loop (DLL) for synchronization [6]. To avoid the generation of the high frequency clock, asynchronous control was adopted in this work [7,10].…”

“…To avoid the generation of the high frequency clock, asynchronous control was adopted in this work [7,10]. Furthermore, the compensation DAC and the summing operation have been realised using switched-capacitor (SC) techniques [6]. The purpose was to avoid the power hungry summing amplifier that would be required otherwise.…”

“…For the CIFB loop filter, it is the double integrating transfer function given by (3). For the SOA loop filter it was given in (6) and is of the following form…”

“…This is straightforward for the CIFB loop filter since b 1 is independent of the feedback coefficients a CT1 and a CT2 . For the SOA loop filter, however, the expression in (6) shows that b 1 is dependent on the two parameters n 1 and n 2 which implement the feedback coefficients a CT1 and a CT2 . The required design procedure is therefore to first determine the two feedback coefficients from DT to CT conversion and then the factors n 1 and n 2 .…”