A 30-b integrated logarithmic number system processor

Yu, Le; Lewis, David

doi:10.1109/4.90098

Cited by 35 publications

(8 citation statements)

References 12 publications

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“…In 1988, Taylor et al have reported [13] an architecture design of the 20-bit logarithmic arithmetic processor. In 1991, Yu and Lewis have reported [30] an architec-ture design of the 30-bit logarithmic arithmetic processor. In 1999, SanGregory's correcting algorithm was implemented that was simple and fast in operation [27].…”

Section: Literature Reviewmentioning

confidence: 99%

An efficient architecture of iterative logarithm multiplier

Nandan¹,

Kanungo²,

Mahajan³

2018

IJET

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Multiplication is one of important arithmetic component for digital signal processing, neural network and image processing. But, it is well known fact that multiplier has most hardware consuming component out of all arithmetic components. Here, it is given a possible solution by using an efficient VLSI architecture of Mitchell's algorithm based Iterative Logarithmic Multiplier (ILM) with modified architecture of Leading One Detector (LOD) and seamless pipelined technique. The proposed work is based on the hardware minimization at the same error cost than of previously reported architectures. We use VHDL to design the existing and proposed Mitchell's algorithm based iterative logarithmic multiplier. Both multipliers design are evaluated with the Synopsys design compiler by using 90 nm CMOS technology and compared the results in terms of Data Arrival Time (DAT), area, power, Area Delay Product (ADP) and energy. The proposed Mitchell's based ILM gives 33.18 %, 39.03 % and 31.62 % less ADP, 25.08 %, 38.08 % and 46.72 % less energy for 8, 16, and 32 bits architecture respectively in comparison of the reported ILM. The importance of LODs and seamless pipeline has been shown in an efficient architecture of Mitchell's based ILM.

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Section: Literature Reviewmentioning

confidence: 99%

An efficient architecture of iterative logarithm multiplier

Nandan¹,

Kanungo²,

Mahajan³

2018

IJET

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“…The algorithm is the Gauss-Seidel fast affine projection (GSFAP) [Albu et al 2002a], which is perhaps one of the most efficient of the fast AP algorithms. To reduce the resource requirements we represent numbers using the logarithmic number system (LNS) [Swartzlander and Alexopoulos 1975;Yu and Lewis 1991;Coleman et al 2000;Coleman et al 2008]. Logarithmic arithmetic allows resource-efficient, low-latency multiplication and division at the cost of slightly more expensive addition and subtraction.…”

Section: Motivationmentioning

confidence: 99%

GSFAP adaptive filtering using log arithmetic for resource-constrained embedded systems

Tichý

Schier

Gregg

2010

ACM Trans. Embed. Comput. Syst.

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Adaptive filters are widely used in many applications of digital signal processing. Digital communications and digital video broadcasting are just two examples. Traditionally, small embedded systems have employed the least computationally intensive filter adaptive algorithms, such as normalized least mean squares (NLMS). This article shows that FPGA devices are a highly suitable platform for more computationally intensive adaptive algorithms. We present an optimized core which implements GSFAP. GSFAP is an algorithm with far superior adaptation properties than NLMS, and with only slightly higher computational complexity. To further optimize resource requirements we use logarithmic arithmetic, rather than conventional floating point, within the custom core. Our design makes effective use of the pipelined logarithmic addition units, and takes advantage of the very low cost of logarithmic multiplication and division. The resulting GSFAP core can be clocked at more than 80MHz on a one million-gate Xilinx XC2V1000-4 device. The core can be used to implement adaptive filters of orders 20 to 1000 performing echo cancellation on speech signals at a sampling rate exceeding 50kHz. For comparison, we implemented a similar NLMS core and found that although it is slightly smaller than the GSFAP core and allows a higher signal sampling rate for the corresponding filter orders, the GSFAP core has adaptation properties that are much superior to NLMS, and that our core can provide very sophisticated adaptive filtering capabilities for resource-constrained embedded systems.

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“…Contemplating the development of LNS-based commercial microprocessors, Lewis et al [10], Paliouras et al [11], and Arnold [12] proposed architectures for LNS-based processors in the late 1990s and early 2000s, but did not present a finished design or extensive simulation results. At about the same time, a European project, initiated by Coleman et al [13], [14], laid down the foundations for the development of such a commercial digital system, dubbed the European logarithmic microprocessor (ELM), which provided performance similar to commercial superscalar pipelined floating-point processors [15].…”

Section: Introductionmentioning

confidence: 99%