A 32 bit logarithmic arithmetic unit and its performance compared to floating-point

Coleman, J.N.; Chester, Ed

doi:10.1109/arith.1999.762839

Cited by 29 publications

(8 citation statements)

References 11 publications

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“…We assumed the range normalization overhead to obtain the maximum accuracy in a system with FXP precision (as compared to a system with FLP or LNS precision); our assumption did not affect the performance of the system. The LNS architecture is faster than the FLP architecture, because the specific LNU used here is three times faster than the FPU; in general, depending on the ratio of multiplication/addition operations, LNU-based architectures can perform 1.5-2.6 times faster than FPU-based architectures [44], [48]. All CMOL architectures are slower than the corresponding CMOS architectures by around 30 ms; this was expected because CMOL nanogrids are slow [1].…”

Section: B Performance/price Results and Discussionmentioning

confidence: 92%

CMOL/CMOS Implementations of Bayesian Polytree Inference: Digital and Mixed-Signal Architectures and Performance/Price

Zaveri

Hammerstrom

2010

IEEE Trans. Nanotechnology

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In this paper, we focus on aspects of the hardware implementation of the Bayesian inference framework within the George and Hawkins' model. This framework is based on Judea Pearl's belief propagation. We then present a "hardware design space exploration" methodology for implementing and analyzing the (digital and mixed-signal) hardware for the Bayesian (polytree) inference framework. This, particular, methodology involves: analyzing the computational/operational cost and the related microarchitecture, exploring candidate hardware components, proposing various custom architectures using both traditional CMOS and hybrid nanotechnology CMOS/nanowire/molecular hybrid (CMOL), and investigating the baseline performance/price of these hardware architectures. The results suggest that hybrid nanotechnology is a promising candidate to implement Bayesian inference. Such implementations utilize the very high density storage/computation benefits of these new nanoscale technologies much more efficiently, for example, the throughput per 858 mm 2 obtained for CMOL-based architectures is 32-40 times better than the TPM for a CMOS based multiprocessor/multifield-programmable gate array system, and almost 2000 times better than the TPM for a single PC implementation. In general, the assessment of such hypothetical hardware architectures provides a baseline for large-scale implementations of Bayesian inference, and guidance for implementing the same using nanogrid structures.

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Section: B Performance/price Results and Discussionmentioning

confidence: 92%

CMOL/CMOS Implementations of Bayesian Polytree Inference: Digital and Mixed-Signal Architectures and Performance/Price

Zaveri

Hammerstrom

2010

IEEE Trans. Nanotechnology

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“…Argument reduction followed by series expansion was applied in [16]. Another approach is to work in logarithmic domain [17,18] where the computation of the inverse square root is straightforward [19,20].…”

Section: Previous Workmentioning

confidence: 99%

Low-Complexity Inverse Square Root Approximation for Baseband Matrix Operations

Salmela

Burian

Jarvinen

et al. 2011

ISRN Signal Processing

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Baseband functions like channel estimation and symbol detection of sophisticated telecommunications systems require matrix operations, which apply highly nonlinear operations like division or square root. In this paper, a scalable low-complexity approximation method of the inverse square root is developed and applied in Cholesky and QR decompositions. Computation is derived by exploiting the binary representation of the fixedpoint numbers and by substituting the highly nonlinear inverse square root operation with a more implementation appropriate function. Low complexity is obtained since the proposed method does not use large multipliers or look-up tables (LUT). Due to the scalability, the approximation accuracy can be adjusted according to the targeted application. The method is applied also as an accelerating unit of an application-specific instruction-set processor (ASIP) and as a software routine of a conventional DSP. As a result, the method can accelerate any fixed-point system where cost-efficiency and low power consumption are of high importance, and coarse approximation of inverse square root operation is required.

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“…Separate the sign and fixed point exponent bits of both operands. D. LNS DivisionAlgorithm [11,18] 1. Separate the sign and fixed point exponent bits of both operands.…”

Section: Lns Arithmetic Unitmentioning

confidence: 99%

“…LNS MultiplicationAlgorithm [11,18] 1. Separate the sign and fixed point exponent bits of both operands.…”

Section: Lns Arithmetic Unitmentioning

confidence: 99%

Implementation of Floating Point and Logarithmic Number System Arithmetic Unit and Their Comparison for Fpga

Kumar¹,

A.K²,

Dasgupta³

2008

Int. Jour. Intel. Elec. Sys.

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Key words:Floating point (FP) representation is commonly used to represent real numbers. Some papers have suggested the use of logarithmic number system (LNS) in addition to floating point. In LNS, a real number is represented as a fixed point logarithm. Therefore multiplication and division in LNS are much simpler in comparison to that in FP, so the LNS can be beneficial if addition and subtraction can be performed with speed and accuracy equal to FP. LNS addition and subtraction requires interpolation technique for which some vales are stored in read only memory (ROM). In this paper, different sizes of ROM are used for addition and subtraction and their performances are compared to the floating point.FPGA, Logarithmic Number Systems, ROM.

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A 32 bit logarithmic arithmetic unit and its performance compared to floating-point

Abstract: As an alternative to floating-point, several

Cited by 29 publications

References 11 publications

CMOL/CMOS Implementations of Bayesian Polytree Inference: Digital and Mixed-Signal Architectures and Performance/Price

CMOL/CMOS Implementations of Bayesian Polytree Inference: Digital and Mixed-Signal Architectures and Performance/Price

Low-Complexity Inverse Square Root Approximation for Baseband Matrix Operations

Implementation of Floating Point and Logarithmic Number System Arithmetic Unit and Their Comparison for Fpga

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