A 33fJ/Step SAR Capacitance-to-Digital Converter Using a Chain of Inverter-Based Amplifiers

Omran, Hesham; Alhoshany, Abdulaziz; Alahmadi, Hamzah; Salama, Khaled N.

doi:10.1109/tcsi.2016.2608905

Cited by 56 publications

(25 citation statements)

References 36 publications

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“…Depending on how the capacitive sensor is connected to the electronic interface circuit, the interface principles can be categorized as (1) capacitive sensors with a grounded target electrode [9][10][11][12][13] ; (2) capacitive sensors with an active target electrode [14][15][16][17][18][19][20][21][22] ; and (3) capacitive sensors with a floating target electrode. 23,24 It should be mentioned that in all categories, to reduce external interference, the sensor plates need to be connected to the interface via a shielded cable.…”

Section: Discussionmentioning

confidence: 99%

“…A performance summary and a comparison with state-of-the-art interfaces [14][15][16][17][18][19][20][21] are shown in Table 1. The energy efficiency of different interfaces is evaluated by using the two well-known energy efficiency figure-of-merits (FOM) as follows [13][14][15][16][17][18][19][20] :…”

Section: Comparison and Discussionmentioning

confidence: 99%

“…where P D is the power consumption of the interface, T M is the conversion time, and CR and ENOB are the capacitance resolution and effective resolution in bits, which are calculated as [13][14][15][16][17][18][19][20] ENOB ¼…”

Section: Comparison and Discussionmentioning

confidence: 99%

“…Moreover, according to the noise analysis in Section 5, for a measurement time of T msm = 100 μs, this can translate into an input-referred capacitance resolution of 126 aF (Equation 19). Moreover, according to the noise analysis in Section 5, for a measurement time of T msm = 100 μs, this can translate into an input-referred capacitance resolution of 126 aF (Equation 19).…”

Section: Studying Design Trade-offsmentioning

confidence: 99%

“…As a design choice, we have selected g m = 0.75 mS and C F = 2 pF, which can satisfy both the noise and accuracy of the interface. Moreover, according to the noise analysis in Section 5, for a measurement time of T msm = 100 μs, this can translate into an input-referred capacitance resolution of 126 aF (Equation 19).…”

Section: Studying Design Trade-offsmentioning

confidence: 99%

See 4 more Smart Citations

Design trade‐offs of a capacitance‐to‐voltage converter with a zoom‐in technique for grounded capacitive sensors

Bijargah

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et al. 2018

Circuit Theory & Apps

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This paper presents a low-power, high-precision capacitance-to-voltage converter (CVC) for grounded capacitive sensors. To measure very small capacitance variations in the presence of a large offset capacitance, a new zoom-in structure is proposed. The major non-idealities of the CVC such as the settling error, charge injection, and parasitic capacitance of the switches are minimized through an optimized design. Accordingly, it is shown that the zoom-in technique can significantly reduce many of these errors. The effect of the parasitic capacitances around the sensor capacitance is significantly reduced by using a switched-capacitor-based active-shielding technique. The interface is designed as an integrated circuit using a standard 0.18-μm CMOS technology. Simulation results show that for a sensor capacitor with a nominal value of 10 pF, variation of only 200 fF, and parasitic capacitance of up to 20 pF, a worst-case capacitance error of 0.2 fF can be achieved by taking into account the layout mismatches and the interconnection effects. The achieved latency is 100 μs, and the CVC consumes only 80 μA from a 2-V power supply. The simulated input capacitance resolution for this latency is 123 aF, which is quite close to our calculated resolution (126 aF). This resolution corresponds to an energy efficiency of 9.82 pJ/Step. A temperature sweep simulation has been performed over the temperature range from −45°C to 125°C to demonstrate the small thermal drift of the designed circuit.

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Section: Discussionmentioning

confidence: 99%

Section: Comparison and Discussionmentioning

confidence: 99%

Section: Comparison and Discussionmentioning

confidence: 99%

Section: Studying Design Trade-offsmentioning

confidence: 99%

Section: Studying Design Trade-offsmentioning

confidence: 99%

See 3 more Smart Citations

Design trade‐offs of a capacitance‐to‐voltage converter with a zoom‐in technique for grounded capacitive sensors

Bijargah

Heidary

Torkzadeh

et al. 2018

Circuit Theory & Apps

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show abstract

Inverter‐based voltage‐controlled and programmable comparators

Sharroush

2020

Circuit Theory & Apps

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Comparators are very important circuits that can be found in a variety of applications, especially comparators whose reference level can be controlled. In this paper, a voltage‐controlled comparator whose reference voltage is controlled by a control voltage and a programmable comparator whose reference voltage is controlled by an input bit pattern are presented. These two comparators are analyzed quantitatively. The performance of the two proposed comparators is verified by simulation using the Berkeley predictive‐technology models (BPTM) of the 45‐, 32‐, 22‐, and 16‐nm complementary metal‐oxide semiconductor (CMOS) technologies with power‐supply voltages, VDD, of 1, 0.9, 0.8, and 0.7 V, respectively. The proposed controlled comparator is compared with the conventional latch‐type comparator from the points of view of the response time, the output amplitude, and the power consumption.

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Low-Power Two-Stage OP-AMP in 16 nm

Agarwal

Dwivedi

2020

Smart Innovation, Systems and Technologies

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A 33fJ/Step SAR Capacitance-to-Digital Converter Using a Chain of Inverter-Based Amplifiers

Cited by 56 publications

References 36 publications

Design trade‐offs of a capacitance‐to‐voltage converter with a zoom‐in technique for grounded capacitive sensors

Design trade‐offs of a capacitance‐to‐voltage converter with a zoom‐in technique for grounded capacitive sensors

Inverter‐based voltage‐controlled and programmable comparators

Low-Power Two-Stage OP-AMP in 16 nm

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