A 370-MHz memory built-in self-test state machine

Abstract

Hardware and simulation results for a 370-MHz memory built-in self-test state machine are presented. Dynamic differential cascode voltage switch logic, unique clocking techniques, and logic pipelining were used to achieve the 370-MHz performance. Testing of multiple SRAMs and content addressable memories is accomplished with deterministic patterns generated by the state machine. Inclusion of a programmable pattern implemented via scan initialization provides test-pattern flexibility. Failing addresses are stored for redundancy implementation.