ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC) 2023
DOI: 10.1109/esscirc59616.2023.10268689
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A 4.8-GHz Time-Interleaved Multi-Reference PLL with 16.1-fs Jitter

Hongzhuo Liu,
Wei Deng,
Haikun Jia
et al.
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Cited by 4 publications
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References 7 publications
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A Compact 21-25 GHz Charge-Domain Fractional-N ADPLL with 168 fs Total RMS Jitter

Tao,
Liu,
Yang
et al. 2024
2024 IEEE European Solid-State Electronics Research Conference (ESSERC)
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A Compact 21-25 GHz Charge-Domain Fractional-N ADPLL with 168 fs Total RMS Jitter

Tao,
Liu,
Yang
et al. 2024
2024 IEEE European Solid-State Electronics Research Conference (ESSERC)
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0
0
0
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A 2.5mW Fully-Passive 2nd-Order Noise-Shaping Bang-Bang PLL with Adaptive DCO Gain Controller Achieving 305-fsrms Jitter and –246.3 dB FoM

Yuan,
Xin,
Yu
et al. 2024
2024 IEEE European Solid-State Electronics Research Conference (ESSERC)
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A 6 GHz RO PLL with −285 dB FOMJitter-N-Area, 130 fs RMS jitter and 0.0016 mm2 Area

Dietl,
Bachmayer,
Brederlow
2024
2024 International Conference on Microelectronics (ICM)
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