IEEE Trans. Circuits Syst. II
 2023
DOI: 10.1109/tcsii.2023.3273290
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A 4-bit 4.5-ns-Latency Pseudo-ReRAM Computing-In-Memory Macro With Self Error-Correcting DTC-Based WL Drivers and 6-bit CDAC-Less Column ADCs Having Ultra-Narrow Pitch

Jongho Kim
1
,
Young H. Oh
2
,
Hyeonsik Kim
3
et al.
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