A 40-GHz static frequency divider with quadrature outputs in 80-nm CMOS

Kromer, C.; Buren, G. von; Sialm, G.; Morf, Thomas; Ellinger, Frank; Jäckel, H.

doi:10.1109/lmwc.2006.882382

Cited by 27 publications

(10 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Fig.9 compares the power-delay product for the various D-F/Fs. As shown in the figure, power-delay product of the proposed D-F/F is much better than those of the previously reported RTD-based NRZ D-F/Fs [6]- [8] and comparable to those of the D-F/Fs using 80 nm-CMOS technology [12]. Since the proposed circuits have been fabricated using RTDs with 2 um minimum feature size, we can expect that speed and power performance can be much improved by using further scaleddown devices.…”

Section: Measurement Results and Discussionmentioning

confidence: 58%

New NRZ-mode resonant tunneling bistable-to-monostable-to-bistable transition logic element operating up to 36 Gb/s

Kim

Yeon

Seo

2007

2007 7th IEEE Conference on Nanotechnology (IEEE NANO)

View full text Add to dashboard Cite

In this paper, we present new resonant tunneling bistable-to-monostable-to-bistable transition logic element with non-return-to-zero (NRZ) mode output. The proposed circuit is composed of resonant tunneling diode (RTD)/high electron mobility transistor (HEMT) series connection (RHS) and RTD/HEMT parallel connection (RHP). Novel high-speed and low-power NRZ delayed flip-flop (D-F/F) operation has been successfully achieved using RTD/HEMT integration technology on an InP substrate. The operation of the fabricated circuit was confirmed up to 36 Gb/s with a very low power dissipation of about 3 mW at a power supply voltage of 0.9 V.

show abstract

Section: Measurement Results and Discussionmentioning

confidence: 58%

New NRZ-mode resonant tunneling bistable-to-monostable-to-bistable transition logic element operating up to 36 Gb/s

Kim

Yeon

Seo

2007

2007 7th IEEE Conference on Nanotechnology (IEEE NANO)

View full text Add to dashboard Cite

show abstract

“…Table I summaries the performances of recently published static frequency dividers. The 50 GHz operating frequency is much higher than those of all 120/130-nm CMOS static frequency dividers [1], [6], [8] and also higher than the 80nm divider's maximum operating frequency reported in [9].…”

Section: Measurement Resultsmentioning

confidence: 88%

Analysis and Design of a 50-GHz 2:1 CMOS CML Static Frequency Divider Based on LC-tank

Skafidas

Evans

et al. 2008

2008 European Microwave Integrated Circuit Conference

View full text Add to dashboard Cite

In this paper, a 2:1 current model logic (CML) frequency divider operating at frequencies up to 50 GHz is reported. A novel circuit topology is employed, which consists of the conventional CML structure with LC-tank components as the output load of the divider. An analytical model of the proposed frequency divider is developed and a new method is presented to estimate the divider's performance. The proposed CML frequency divider contains four spiral inductors and is fabricated on standard 130-nm CMOS technology. The division range of the proposed divider was measured from 30 GHz to 50 GHz with 11.7 mW power dissipation at a 1.5-V supply voltage.

show abstract

“…Using a standard divider topology (see e.g. [7]), this building block generates also the needed quadrature components.…”

Section: Synchronous Demodulation Of M-qam Signalsmentioning

confidence: 99%

Si/SiGe ICs for ultra-broadband communications: The analog signal processing perspective

Schumacher

Ulusoy

Liu

et al. 2013

2013 IEEE MTT-S International Microwave Symposium Digest (MTT)

View full text Add to dashboard Cite

Digital signal processing is the de facto standard in wireless communications. Facilitated by the unprecedented increase in computing power, it offers excellent performance in tasks such as channel equalization, demodulation, or error correction. With increasing bitrates in wireless links, towards 10 Gb/s and above, this development needs to be re-assessed as analog techniques may offer the required performance at much reduced power and cost. This paper will focus on the receiver part of the channel, discussing how analog signal processing techniques can be successfully applied to demodulation and channel equalization.

show abstract

A 40-GHz static frequency divider with quadrature outputs in 80-nm CMOS

Cited by 27 publications

References 5 publications

New NRZ-mode resonant tunneling bistable-to-monostable-to-bistable transition logic element operating up to 36 Gb/s

New NRZ-mode resonant tunneling bistable-to-monostable-to-bistable transition logic element operating up to 36 Gb/s

Analysis and Design of a 50-GHz 2:1 CMOS CML Static Frequency Divider Based on LC-tank

Si/SiGe ICs for ultra-broadband communications: The analog signal processing perspective

Contact Info

Product

Resources

About