A 4Gb 2b/cell NAND Flash Memory with Embedded 5b BCH ECC for 36MB/s System Read Throughput

Micheloni, Rino; Ravasio, Roberto; Marelli, Alessia; Alice, Electa; Altieri, V.; Bovino, A.; Crippa, Luca; Martino, E. Di; D'Onofrio, L.; Gambardella, Antonio; Grillea, E.; Guerra, G.; Kim, D.; Missiroli, C.; Motta, I.; Prisco, A.; Ragone, G.; Sangalli, M.; Sauro, P.; Scotti, M.; Won, Soyoung

doi:10.1109/isscc.2006.1696082

Cited by 61 publications

(32 citation statements)

References 1 publication

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“…BCH codes are widely used in today's flash controllers to detect and correct multi-bit errors [28] [29]. Out of n total bits in a code word, the first k bits are data bits, and the remaining (n-k) bits are the error correction information to protect the data bits.…”

Section: Minimizing the Error Correction Latencymentioning

confidence: 99%

Data retention in MLC NAND flash memory: Characterization, optimization, and recovery

Cai

Luo

Haratsch³

et al. 2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

235

267

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Abstract-Retention errors, caused by charge leakage over time, are the dominant source of flash memory errors. Understanding, characterizing, and reducing retention errors can significantly improve NAND flash memory reliability and endurance. In this paper, we first characterize, with real 2y-nm MLC NAND flash chips, how the threshold voltage distribution of flash memory changes with different retention age -the length of time since a flash cell was programmed. We observe from our characterization results that 1) the optimal read reference voltage of a flash cell, using which the data can be read with the lowest raw bit error rate (RBER), systematically changes with its retention age, and 2) different regions of flash memory can have different retention ages, and hence different optimal read reference voltages. Based on our findings, we propose two new techniques. First, Retention Optimized Reading (ROR) adaptively learns and applies the optimal read reference voltage for each flash memory block online. The key idea of ROR is to periodically learn a tight upper bound, and from there approach the optimal read reference voltage. Our evaluations show that ROR can extend flash memory lifetime by 64% and reduce average error correction latency by 10.1%, with only 768 KB storage overhead in flash memory for a 512 GB flash-based SSD. Second, Retention Failure Recovery (RFR) recovers data with uncorrectable errors offline by identifying and probabilistically correcting flash cells with retention errors. Our evaluation shows that RFR reduces RBER by 50%, which essentially doubles the error correction capability, and thus can effectively recover data from otherwise uncorrectable flash errors.

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Section: Minimizing the Error Correction Latencymentioning

confidence: 99%

Data retention in MLC NAND flash memory: Characterization, optimization, and recovery

Cai

Luo

Haratsch³

et al. 2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

235

267

View full text Add to dashboard Cite

show abstract

“…The choice of the most suitable error correcting scheme is tightly application dependent. For this reason, practical ECC solutions are typically market segment-specific and range from derivatives of the Hamming code [2] to the BCH [8] or the Reed-Solomon code [9].…”

Section: Introductionmentioning

confidence: 99%

A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories

Zambelli¹,

Indaco²,

Fabiano³

et al. 2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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In spite of the mature cell structure, the memory controller architecture of Multi-level cell (MLC) NAND Flash memories is evolving fast in an attempt to improve the uncorrected/miscorrected bit error rate (UBER) and to provide a more flexible usage model where the performance-reliability trade-off point can be adjusted at runtime. However, optimization techniques in the memory controller architecture cannot avoid a strict trade-off between UBER and read throughput. In this paper, we show that co-optimizing ECC architecture configuration in the memory controller with program algorithm selection at the technology layer, a more flexible memory sub-system arises, which is capable of unprecedented trade-offs points between performance and reliability.

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“…As the semiconductor geometry shrinks, the error performance of NAND Flash memory becomes worse, thus it is greatly needed to increase the reliability by using memory signal processing and forward-error correction (FEC) methods. Among various FEC codes, Bose-Chaudhuri-Hocquenghem (BCH) and Reed-Solomon (RS) codes have widely been used for NAND Flash error correction [1][2][3]. However, because of severe performance degradation of recent NAND Flash memory devices, more advanced FEC codes are needed.…”

Section: Introductionmentioning

confidence: 99%

Low-energy error correction of NAND Flash memory through soft-decision decoding

Kim

Sung

2012

EURASIP J. Adv. Signal Process.

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The raw bit error rate of NAND Flash memory increases as the semiconductor geometry shrinks for high density, which makes it very necessary to employ a very strong error correction circuit. The soft-decision-based error correction algorithms, such as low-density parity-check (LDPC) codes, can enhance the error correction capability without increasing the number of parity bits. However, soft-decision error correction schemes need multiple precision data, which obviously increases the energy consumption in NAND Flash memory for more sensing operations as well as more data output. We examine the energy consumption of a NAND Flash memory system with an LDPC code-based soft-decision error correction algorithm. The energy consumed at multiple-precision NAND Flash memory as well as the LDPC decoder is considered. The output precision employed is 1.0, 1.4, 1.7, and 2.0 bits per data. In addition, we also propose an LDPC decoder-assisted precision selection method that needs virtually no overhead. The experiment was conducted with 32-nm 128-Gbit 2-bit multi-level cell NAND Flash memory and a 65-nm LDPC decoding VLSI.

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A 4Gb 2b/cell NAND Flash Memory with Embedded 5b BCH ECC for 36MB/s System Read Throughput

Cited by 61 publications

References 1 publication

Data retention in MLC NAND flash memory: Characterization, optimization, and recovery

Data retention in MLC NAND flash memory: Characterization, optimization, and recovery

A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories

Low-energy error correction of NAND Flash memory through soft-decision decoding

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