A 50-Gb/s differential transimpedance amplifier in 65nm CMOS technology

Abstract

A 50-Gb/s differential transimpedance amplifier is realized in a standard 65nm CMOS process, which exploits asymmetric transformer peaking technique for bandwidth extension and employs a modified regulated-cascode input stage with a shunt-feedback common-source amplifier for differential signaling. Measured results demonstrate 52-dB transimpedance gain, 50-GHz bandwidth for 50fF photodiode capacitance, -12.3dBm sensitivity for 10 -12 BER, and 49.2-mW power dissipation from a single 1.2-V supply. To the best of authors' knowledge, this chip achieves the fastest operation speed among the recently reported gigabit CMOS transimpedance amplifiers. The chip occupies the total area of 1.2×0.8mm 2 including pad.

CMOS Integrated Circuits for Various Optical Applications

“…The group delay variations of the MC-TIA were measured to be within AE10 ps. The single-ended integrated output noise voltage (1.42 mV rms ) of the MC-TIA was measured by using Agilent DCA 86100D oscilloscope in the absence of input signals [27,29,32]. (10) Then, the average input-referred noise current spectral density is given by…”

“…The latter can hardly remove the DC offset between the TIA core and the dummy, let alone the increase of power consumption. Recently, we have presented a fully differential modified regulated cascode TIA in [27]. Yet, it suffered inherent noise degradation because of the current-mode common-gate input configuration.…”

A low-noise 71-dBΩ transimpedance 31-GHz bandwidth optical receiver with automatic gain control in 0.13-µm SiGe BiCMOS

“…Additionally, the chip occupies relatively small area compared with works implemented in SiGe processes. Peaking inductors are employed in [4,5,6,11,17,24,25,26] to extend bandwidth. Apart from that, technologies in [4,5] are faster than that of the proposed work.…”

“…Additionally, it is difficult to trade off transimpedance against bandwidth in high-speed applications [9]. By adopting passive networks to tune out parasitic effects [10,11] or introducing post-amplifier equalization technique [12], the negative impacts of the issues can be mitigated. A CB or CG TIA can be another alternative to relieve the dependence, while lower transimpedance limit and fewer degrees of freedom for noise optimization are unfavorable [9,13,14].…”

“…Automatic gain control (AGC) potentially reduces jitter and pulse-width distortion under circumstances of large input current swing. Several power-efficient 40-Gb/s and beyond TIAs and RXs implemented in CMOS technology were reported [11,16,17,18,19]. In these designs, series or shunt inductive peaking techniques were employed for bandwidth extension.…”