A 56 mW Continuous-Time Quadrature Cascaded $\Sigma\Delta$ Modulator With 77 dB DR in a Near Zero-IF 20 MHz Band

Breems, Lucien J.; Rutten, R. J.; Veldhoven, Robert H. M. van; Weide, G. van der

doi:10.1109/jssc.2007.908765

Cited by 94 publications

(23 citation statements)

References 15 publications

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“…Assuming the quantization noise to be uniformly distributed in with variance , an estimation of the maximum value of for a sinusoidal input of frequency and amplitude is given by (7) where . The factor accounts for the relation between the total power of a signal and its maximum amplitude.…”

Section: Minimum Number Of Levels At the Quantizermentioning

confidence: 99%

“…For the uniformly distributed noise of power , is three. Due to the statistical distribution of , in (7). As long as is smaller than , the quantizer in Fig.…”

Section: Minimum Number Of Levels At the Quantizermentioning

confidence: 99%

“…Analog-to-digital converters (ADCs) based on CT SDMs extend the input frequency range from a few 100 kHz up to a few 10 MHz and prove to be a power-efficient solution [2]- [7]. Like the rest of the SDM-based converters, CT SDMs are suitable for integration using CMOS technologies due to their relaxed requirements on the analog components [8].…”

Section: Introductionmentioning

confidence: 99%

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Continuous-Time Sigma–Delta Modulator With a Fast Tracking Quantizer and Reduced Number of Comparators

Colodro

Torralba

2010

IEEE Trans. Circuits Syst. I

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Using a tracking analog-to-digital converter as the quantizer of a sigma-delta modulator (SDM) has been shown to be an efficient method of reducing the number of comparators. In this paper, a new continuous-time (CT) SDM is proposed where a large reduction in the number of comparators is obtained by clocking the quantizer tracking loop at a high frequency rate. For a given example, the number of bits of the quantizer is shown to be reduced from five in the original multibit modulator to only one in a quantizer with tracking sampled at three times the original sampling frequency. In addition, the output of the tracking quantizer can be downsampled so that the modulator output has the same resolution and sampling rate as the original modulator. In this way, the design of the digital-to-analog converters in the feedback loop and the decimator filter at the modulator output are not penalized. Furthermore, the digital integrator of the tracking loop can be removed by taking profit of the last CT integrator in the forward path. Finally, the signal component in the forward path can be attenuated by adding a direct path from the modulator input to the last integrator input. As a result, the output swing of the integrators is reduced, improving the linearity of the whole modulator. The new modulators are analyzed and extensive theoretical and simulation results are provided.

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Section: Minimum Number Of Levels At the Quantizermentioning

confidence: 99%

“…For the uniformly distributed noise of power , is three. Due to the statistical distribution of , in (7). As long as is smaller than , the quantizer in Fig.…”

Section: Minimum Number Of Levels At the Quantizermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Continuous-Time Sigma–Delta Modulator With a Fast Tracking Quantizer and Reduced Number of Comparators

Colodro

Torralba

2010

IEEE Trans. Circuits Syst. I

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“…It is also used in analog-to-digital conversion [35][36][37][38], in phase-locked loops [39][40][41][42][43][44][45][46][47][48][49], and as a source to generate dithering signals [50][51][52][53][54][55][56], to segment the DAC further [57,58] and in multiple-input, multiple-output transceivers [59], etc. All of the above signal processing blocks are used for narrow-, wideand ultra-wide-band applications like digital audio [60][61][62], handsets [63][64][65], biomedical [66,67], TV [68][69][70], digital radio tuners [71,72] and wireless infrastructures [73][74][75].…”

Section: Introductionmentioning

confidence: 99%

Complexity and Power Reduction in Digital Delta-Sigma Modulators

Afzal

2015

Linköping Studies in Science and Technology. Dissertations

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Papers A and C are reprinted with permission from IEEE.Cover figure is an illustration of the digital cascaded error-feedback modulator.Printed by LiU-Tryck, Linköping, Sweden 2014 To my parents and teachers AbstractA number of state-of-the-art low power consuming digital delta-sigma modulator (∆Σ) architectures for digital-to-analog converters (DAC) are presented in this thesis. In an oversampling ∆Σ DAC, the primary job of the modulator is to reduce the word length of the digital control signal to the DAC and spectrally shape the resulting quantization noise. Among the ∆Σ topologies, error-feedback modulators (EFM) are well suited for so called digital to digital modulation In order to meet the demands, various modifications to the conventional EFM architectures have been proposed. It is observed that if the internal and external digital signals of the EFM are not properly scaled then not only the design itself but also the signal processing blocks placed after it, may be over designed. In order to avoid the possible wastage of resources, a number of scaling criteria are derived. In this regard, the total number of signal levels of the EFM output is expressed in terms of the input scale, the order of modulation and the type of the loop filter.Further on, it is described that the architectural properties of a unit elementbased DAC allow us to move some of the digital processing of the EFM to the analog domain with no additional hardware cost. In order to exploit the architectural properties, digital circuitry of an arbitrary-ordered EFM is split into two parts: one producing the modulated output and another producing the filtered quantization noise. The part producing the modulated output is removed after representing the EFM output with a set of encoded signals. For both the conventional and the proposed EFM architectures, the DAC structure remains unchanged. Thus, savings are obtained since the bits to be converted are not accumulated in the digital domain but instead fed directly to the DAC.A strategy to reduce the hardware of conventional EFMs has been devised recently that uses multiple cascaded EFM units. We applied the similar approach but used several cascaded modified EFM units. The compatibility issues among the units (since the output of each proposed EFM is represented by the set of encoded signals) are resolved by a number of architectural modifications. The digital processing is distributed among each unit by splitting the primary input bus. It is shown that instead of cascading the EFM units, it is enough to cascade their loop filters only. This leads not only to area reduction but also to the reduction of power consumption and critical path.All of the designs are subjected to rigorous analysis and are described mathev vi Abstract matically. The estimates of area and power consumption are obtained after synthesizing the designs in a 65 nm standard cell library provided by the foundry. Populärvetenskaplig sammanfattning vii viiiPopulärvetenskaplig sammanfattning I denna avhandling presenteras e...

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“…A cascaded CT DSM design is far more sensitive to the time-constant variation than a single-stage design. Previous works use off-line calibration techniques to minimize the in-band noise in the digital output [1]− [3]. They achieved a higher tuning accuracy than conventional master-slave approaches did, but the modulator input should be forced to ground while calibrating.…”

Section: Introductionmentioning

confidence: 99%

A self-calibrated 2–1–1 cascaded continuous-time ΔΣ modulator

Kamiishi

Shu

Tomioka

et al. 2009

2009 IEEE Custom Integrated Circuits Conference

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A 2-1-1 cascaded continuous-time ΔΣ modulator (DSM) is self-calibrated with LMS-based adaptation. Its noise cancellation filter (NCF) is derived using a parameter-based continuous-time (CT) to discrete-time (DT) transform. These techniques reduce the quantization noise leakage due to the mismatch between analog modulator and digital NCF. A 0.18-μm CMOS prototype operating at 360MHz with a 1-V pp full-scale demonstrates a leakage noise spectral density below 10nV/√Hz over a 30-MHz bandwidth after the capacitors in the Gm-C loop filters are self-trimmed with a 1.1% step. This level of noise leakage is well below the noise floor of most CT DSM designs.

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A 56 mW Continuous-Time Quadrature Cascaded $\Sigma\Delta$ Modulator With 77 dB DR in a Near Zero-IF 20 MHz Band

Cited by 94 publications

References 15 publications

Continuous-Time Sigma–Delta Modulator With a Fast Tracking Quantizer and Reduced Number of Comparators

Continuous-Time Sigma–Delta Modulator With a Fast Tracking Quantizer and Reduced Number of Comparators

Complexity and Power Reduction in Digital Delta-Sigma Modulators

A self-calibrated 2–1–1 cascaded continuous-time ΔΣ modulator

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A 56 mW Continuous-Time Quadrature Cascaded $\Sigma\Delta$ Modulator With 77 dB DR in a Near Zero-IF 20 MHz Band

Cited by 94 publications

References 15 publications

Continuous-Time Sigma–Delta Modulator With a Fast Tracking Quantizer and Reduced Number of Comparators

Continuous-Time Sigma–Delta Modulator With a Fast Tracking Quantizer and Reduced Number of Comparators

Complexity and Power Reduction in Digital Delta-Sigma Modulators

A self-calibrated 2&#x2013;1&#x2013;1 cascaded continuous-time &#x0394;&#x03A3; modulator

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A self-calibrated 2–1–1 cascaded continuous-time ΔΣ modulator