A 6-Bit 800-MS/s Pipelined A/D Converter with Open-Loop Amplifiers

Shen, Ding-Lan; Lee, Tai-Cheng

doi:10.1109/vlsic.2006.1705346

Cited by 7 publications

(10 citation statements)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The resulting sample-rate of 2.4 GS/s is, to the authors' best knowledge, significantly faster than any previously reported single-channel pipeline ADC [1][2] [3].…”

Section: Introductionmentioning

confidence: 83%

A 2.4 GS/s, 4.9 ENOB at Nyquist, single-channel pipeline ADC in 65nm CMOS

Sundström

Svensson

Alvandpour

2010

2010 Proceedings of ESSCIRC

View full text Add to dashboard Cite

This paper presents a high-speed single channel pipeline analog-to-digital converter sampling at 2.4 GS/s which, to the authors' best knowledge, is the fastest reported for pipeline converters. The use of a time-borrowing clocking scheme eliminates the comparator latency from the critical path and together with the use of fast open-loop current-mode amplifiers the high sample rate is achieved. Implemented in a 65nm general purpose CMOS technology the effective number of bits is above 4.7 in the Nyquist band, being 5.4 and 4.9 at DC and Nyquist respectively. This shows that very fast pipeline ADCs are possible to implement as key building blocks in interleaved structures.

show abstract

“…The resulting sample-rate of 2.4 GS/s is, to the authors' best knowledge, significantly faster than any previously reported single-channel pipeline ADC [1][2] [3].…”

Section: Introductionmentioning

confidence: 83%

A 2.4 GS/s, 4.9 ENOB at Nyquist, single-channel pipeline ADC in 65nm CMOS

Sundström

Svensson

Alvandpour

2010

2010 Proceedings of ESSCIRC

View full text Add to dashboard Cite

show abstract

“…Gain mismatch should be kept below ±5% to meet target SNDR of 56 dB. A simple differential pair [10] was used as an amplifier and source degeneration has been employed to linearize the amplifier's gain. In addition, the ADC input range is limited well below the supply, i.e., 0.88 V pp to reduce mismatch errors.…”

Section: B Amplifier Gain Mismatch Effect On Interpolationmentioning

confidence: 99%

A 10-bit 200-MS/s Zero-Crossing-Based Pipeline ADC in 0.13-$\mu $ m CMOS Technology

Chu

Kim

Lee

2015

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

This brief presents a zero-crossing-based pipeline analog-todigital converter (ADC) architecture that can effectively reduce hardware complexity and power consumption for high-speed ADCs. The ADC uses only simple open-loop amplifiers for residue amplification. Using modified sliding interpolation and subranging techniques, the number of amplifiers is reduced by 60%. A 10-bit 200-MS/s ADC, employing the architecture and other techniques, such as double sampling, digital error correction, and source degeneration, is fabricated in 0.13-µm CMOS process and occupies a die area of 0.7 mm 2 . The differential and integral nonlinearity of the ADC are less than 0.83/−0.47 and 1.05/−0.7 LSB, respectively. With a 1.5-MHz full-scale input, the ADC achieves 56.5-dB signal-to-noise plus distortion ratio, 71.8-dB spurious free dynamic range, and 9.1 effective number of bits at full sampling rate while dissipating 38 mW from a 1.2-V supply.

show abstract

“…As outlined, there are limitations in obtaining desired performance and the solution can be the attempt to obtain those performance with the evolving technology or to invent new algorithms or new architectures that fit the advantageous feature of the new processes. Since speed is one of the key advantages, methods that trade speed with other paramenters are good candidates for future developments [13][14][15][16][17][18].…”

Section: A New Algorithms and Architecturesmentioning

confidence: 99%

High-performance data converters: Trends, process technologies and design challenges

Maloberti

2008

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems

View full text Add to dashboard Cite

High-performance electronic systems use more and more use high-performance data converters for improving and shaping the architecture and opening new application perspectives. The current and future trend depends on old and new factors that include global economy, technology evolution and marketing. All these elements are driving forces and create new challenges for the designer that answer the requests of new applications by exploiting the advantages and limiting the drawbacks due to the amazing growth of process technologies.

show abstract

A 6-Bit 800-MS/s Pipelined A/D Converter with Open-Loop Amplifiers

Cited by 7 publications

References 15 publications

A 2.4 GS/s, 4.9 ENOB at Nyquist, single-channel pipeline ADC in 65nm CMOS

A 2.4 GS/s, 4.9 ENOB at Nyquist, single-channel pipeline ADC in 65nm CMOS

A 10-bit 200-MS/s Zero-Crossing-Based Pipeline ADC in 0.13-$\mu $ m CMOS Technology

High-performance data converters: Trends, process technologies and design challenges

Contact Info

Product

Resources

About