A 6-GHz ROM suitable for DDFS application in GaAs HBT technology

Abstract

Read-only memory (ROM) is widely implemented as a phase-to-amplitude mapping block in direct digital frequency synthesizers (DDFS). This paper derives an equivalent model for the ROM in a DDFS to analyze and reduce the access time that is critical to the performance of the DDFS. Moreover, the signal skew observed in the simulation waveform is illustrated. The proposed 64×3-bit ROM is integrated as a part of an 8-bit DDFS, which operates functionally at 6 GHz. Measurement results demonstrate the improvement in the spur free dynamic range. Direct digital frequency synthesizers (DDFS) are widely used in communication systems, chirp radar systems, and phase array antennas. To exploit DDFSs in broadband communication systems, DDFS designs operating at GHz-range clock frequencies are required. A direct digital synthesizer can be implemented from a phase accumulator, a phaseto-amplitude mapping block, and a digital-to-analog converter. The phase-to-amplitude mapping block is the key to a high performance DDFS. Many architectures and designs for the phase-to-amplitude mapping block in a DDFS have been reported in the literature. Phase-to-amplitude mapping methods are mainly based on ROM-based designs [1], computational mapping designs [2,3], or both [4-6]. The increasing demand for higher speed DDFS circuits and the frequency limitations in CMOS technologies have necessitated the development of DDFSs implemented using heterojunction bipolar transistor (HBT) technology. Although indium phosphide (InP) HBT based circuits tend to work at a high frequency, high cost and low yield have limited the development of InP HBT based large scale integrated (LSI) circuits. Gallium arsenide (GaAs) HBT combining high frequency and high yield with a moderate price, shows prominent application in mixed-signal integrated circuits with a high level of complexity, such as the ultrahigh speed DDFS with high spur free dynamic range (SFDR).Comparing to a DDFS with computational mapping [3], the one with both ROM and computational mapping [7] was found to have a higher SFDR. However, the ROM is often the limiting factor for the high speed of a DDFS, because it has to support clock rates in the order of two-and-half times the synthesized frequency [8]. Many technologies have been adopted to realize a high speed ROM with large size. The fastest CMOS ROM reported, operates at a frequency up to 1.1 GHz [9]. A 64-bit, 5-GHz read-write look-up table (LUT) has been implemented in GaAs HBT [10], while an InP HBT 36-GHz, 16×6-bit ROM test circuit has also been