A 60 MHz 240 mW MPEG-4 video-phone LSI with 16 Mb embedded DRAM

Nishikawa, Takafumi; Takahashi, Masafumi; Hamada, M.; Takayanagi, T.; Arakida, Hideho; Machida, Nobuya; Yamamoto, Hideki; Fujiyoshi, Toshihide; Matsumoto, Y.; Yamagishi, O.; Samata, T.; Asano, A.; Terazawa, T.; Ohmori, Kenji; Shirakura, J.; Watanabe, Yoshinori; Nakamura, Hiroki; Minami, Shigenobu; Kuroda, Tadahiro; Furuyama, T.

doi:10.1109/isscc.2000.839762

Cited by 38 publications

(14 citation statements)

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“…As such, it incorporates more flexibility then will be needed or even effective in a final system. In spite of this limitation, the test architecture, including reconfiguration overhead and the inefficiencies of standard cell implementation, has comparable performance specifications to recent implementations by Toshiba [8]and Matsushita [9] . Table 1 …”

Section: Parameterized Motion Estimation Architecturementioning

confidence: 98%

Dynamically Parameterized Algorithms and Architectures to Exploit Signal Variations

Jain

Laffely

Burleson

et al. 2004

The Journal of VLSI Signal Processing-Systems for Signal, Image

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Signal processing algorithms and architectures can use dynamic reconfiguration to exploit variations in signal statistics with the objectives of improved performance and reduced power. Parameters provide a simple and formal way to characterize incremental changes to a computation and its computing mechanism. This paper develops a framework for dynamic parameterization and applies it to MPEG-4 motion estimation.A novel motion estimation architecture facilitates the dynamic variation of parameters to achieve power-compression tradeoffs. Our work shows that parameter variation in motion estimation helps achieve power reduction by an order of magnitude, trading off higher ii

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Section: Parameterized Motion Estimation Architecturementioning

confidence: 98%

Dynamically Parameterized Algorithms and Architectures to Exploit Signal Variations

Jain

Laffely

Burleson

et al. 2004

The Journal of VLSI Signal Processing-Systems for Signal, Image

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“…It shows that MCTF requires high system memory bandwidth due to its bidirectional prediction, update stage and multilevel structure. Besides, as shown in [7], system memory access can occupy more than 60% total power of a video system. Therefore, an efficient MCTF architecture should not only be area-efficient but also require low system memory bandwidth.…”

Section: Introductionmentioning

confidence: 99%

Efficient Architecture Design of Motion-Compensated Temporal Filtering/Motion Compensated Prediction Engine

Chen

Cheng

Chuang

et al. 2008

IEEE Trans. Circuits Syst. Video Technol.

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Abstract-Since motion-compensated temporal filtering (MCTF) becomes an important temporal prediction scheme in video coding algorithms, this paper presents an efficient temporal prediction engine which not only is the first MCTF hardware work but also supports traditional motion-compensated prediction (MCP) scheme to provide computation scalability. For the prediction stage of MCTF and MCP schemes, modified extended double current Frames is adopted to reduce the system memory bandwidth, and a frame-interleaved macroblock pipelining scheme is proposed to eliminate the induced data buffer overhead. In addition, the proposed update stage architecture with pipelined scheduling and motion estimation (ME) -

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“…According to the data provided in [3], the external access in a MPEG-4 encoding system supporting QCIF resolution consumes 651mW with 0.25um process. Assuming equal According the average data reduction ratio listed in Table I, the proposed EC engine can save 109mW, 114mW, and 136mW in 0.18um process with lossless mode, half-size mode, and quarter-size mode, respectively.…”

Section: Resultsmentioning

confidence: 99%

“…Assuming equal According the average data reduction ratio listed in Table I, the proposed EC engine can save 109mW, 114mW, and 136mW in 0.18um process with lossless mode, half-size mode, and quarter-size mode, respectively. Because the implemented EC codec can process video with CIF resolution that is 4× as the QCIF resolution in [3], the power saving introduced by this EC codec can be actually even larger. Compared with the 2mW power consumption of EC engine while processing video with CIF format, the power saving is quite huge.…”

Section: Resultsmentioning

confidence: 99%

Multi-mode embedded compression codec engine for power-aware video coding system

Cheng¹,

Tseng²,

Huang³

et al.

IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.

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Abstract-In a typical portable multi-media system, external access, which is usually dominated by block-based video content, induces more than half of total system power. Embedded compression (EC) effectively reduces external access caused by video content by reducing the data size. In this paper, an algorithm and a hardware architecture of a new type EC codec engine with multiple modes are presented. Lossless mode, and lossy modes with rate control modes and quality control modes are all supported by single algorithm. The proposed four-tree pipelining scheme can reduce 83% latency and 67% buffer size between transform and entropy coding. The proposed EC codec engine can save 62%, 66%, and 77% external access at lossless mode, half-size mode, and quarter-size mode and can be used in various system power conditions. With TSMC 0.18 µm 1P6M CMOS logic process, the proposed EC codec engine can encode or decode CIF 30 frame per second video data and achieve power saving of more than 109mW. The EC codec engine itself consumes only 2mW power.

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A 60 MHz 240 mW MPEG-4 video-phone LSI with 16 Mb embedded DRAM

Cited by 38 publications

References 0 publications

Dynamically Parameterized Algorithms and Architectures to Exploit Signal Variations

Dynamically Parameterized Algorithms and Architectures to Exploit Signal Variations

Efficient Architecture Design of Motion-Compensated Temporal Filtering/Motion Compensated Prediction Engine

Multi-mode embedded compression codec engine for power-aware video coding system

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