A 64-point Fourier transform chip for video motion compensation using phase correlation

Chiu, Chian‐Song; Hui, Wing Sze; Ding, T.J.; McCanny, J.V.

doi:10.1109/jssc.1996.542320

Cited by 29 publications

(2 citation statements)

References 17 publications

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“…This is shown in Fig. 15 and is required by (3). The real part of the equalizer coefficient m r is obtained by dividing the real part of the pilot symbol with the summation of H sq and the factor λ.…”

Section: Division Modulementioning

confidence: 99%

Low-Power-Adaptive MC-CDMA Receiver Architecture

Hasan¹,

Arslan²,

John³

2007

ETRI J

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Mohd. Hasan et al. 79This paper proposes a novel concept of adjusting the hardware size in a multi-carrier code division multiple access (MC-CDMA) receiver in real time as per the channel parameters such as delay spread, signal-to-noise ratio, transmission rate, and Doppler frequency. The fast Fourier transform (FFT) or inverse FFT (IFFT) size in orthogonal frequency division multiplexing (OFDM)/MC-CDMA transceivers varies from 1024 points to 16 points. Two low-power reconfigurable radix-4 256-point FFT processor architectures are proposed that can also be dynamically configured as 64-point and 16-point as per the channel parameters to prove the concept. By tailoring the clock of the higher FFT stages for longer FFTs and switching to shorter FFTs from longer FFTs, significant power saving is achieved. In addition, two 256 sub-carrier MC-CDMA receiver architectures are proposed which can also be configured for 64 sub-carriers in real time to prove the feasibility of the concept over the whole receiver.

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Section: Division Modulementioning

confidence: 99%

Low-Power-Adaptive MC-CDMA Receiver Architecture

Hasan¹,

Arslan²,

John³

2007

ETRI J

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“…9(b). [5][6][7][8][9]. Our previous dual rate FFT/IFFT architecture [5] focused on 802.11a application is used for comparison with this highly pipelined structure.…”

Section: Simulation and Comparisonmentioning

confidence: 99%

A High-speed Highly Pipelined 2N-point FFT Architecture For A Dual Ofdm Processor

Lin

Chang

Chen

et al.

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.

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high-speed highly pipelined dual-input FFT/IFFT architecture efficiently sharing hardware is proposed for MIMO WLAN communication systems. It reduces the hardware complexity to enhance the throughput of the FFT/IFFT processor to be applied to IEEE 802.11n WLAN system or beyond. The area and the power consumption of the proposed design is 0.66mm 2 and 97mW at 200MHz operation frequency with dual input/output 64-point FFT/IFFT sequences using TSMC 0.18 m 1P6M technology at supply voltage of 1.8V.

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From Bit Level Systolic Arrays to HDTV Processor Chips

Woods¹,

McCanny²,

McWhirter

2007

J Sign Process Syst Sign Image Video Technol

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The initial part of this paper reviews the early challenges (c 1980) in achieving real-time silicon implementations of DSP computations. In particular, it discusses research on application specific architectures, including bit level systolic circuits that led to important advances in achieving the DSP performance levels then required. These were many orders of magnitude greater than those achievable using programmable (including early DSP) processors, and were demonstrated through the design of commercial digital correlator and digital filter chips. As is discussed, an important challenge was the application of these concepts to recursive computations as occur, for example, in Infinite Impulse Response (IIR) filters. An important breakthrough was to show how fine grained pipelining can be used if arithmetic is performed most significant bit (msb) first. This can be achieved using redundant number systems, including carry-save arithmetic. This research and its practical benefits were again demonstrated through a number of novel IIR filter chip designs which at the time, exhibited performance much greater than previous solutions. The architectural insights gained coupled with the regular nature of many DSP and video processing computations also provided the foundation for new methods for the rapid design and synthesis of complex DSP System-on-Chip (SoC), Intellectual Property (IP) cores. This included the creation of a wide portfolio of commercial SoC video compression cores (MPEG2, MPEG4, H.264) for very high performance applications ranging from cell phones to High Definition TV (HDTV). The work provided the foundation for systematic methodologies, tools and design flows including high-level design optimizations based on^algorithmic engineering^and also led to the creation of the Abhainn tool environment for the design of complex heterogeneous DSP platforms comprising processors and multiple FPGAs. The paper concludes with a discussion of the problems faced by designers in developing complex DSP systems using current SoC technology.

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A 64-point Fourier transform chip for video motion compensation using phase correlation

Cited by 29 publications

References 17 publications

Low-Power-Adaptive MC-CDMA Receiver Architecture

Low-Power-Adaptive MC-CDMA Receiver Architecture

A High-speed Highly Pipelined 2N-point FFT Architecture For A Dual Ofdm Processor

From Bit Level Systolic Arrays to HDTV Processor Chips

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