A 65-nm low-power high-linearity ΣΔ ADC for audio applications

Abstract

This paper presents a low-power high linearity Σ∆ analog-to-digital converter (ADC) for audio applications. By adopting low noise large output swing operational amplifiers in a 2-1 cascaded modulator, not only can the noise floor be reduced, but the input signal range can also be enlarged. A low-power, area-efficient digital decimation filter was also designed to decrease the area and the power cost. The ADC was fabricated in the SMIC 65 nm single-poly-eight-metal (1P8M) mixed-signal complementary metal-oxide-semiconductor (CMOS) process with a die area of 0.36 mm 2 . Measurement results showed that a 90 dB peak signal to noise plus distortion ratio (SNDR) and a 93 dB dynamic range (DR) were achieved over the 22.05 kHz audio band. The power dissipation was 2.2 mW from 1.2 V power supply, which is suitable for audio codec applications.