A 7-ns 140-mW 1-Mb CMOS SRAM with current sense amplifier

Sasaki, K.; Ishibashi, Koji; Ueda, Kazuhiro; Komiyaji, K.; Yamanaka, Toshiaki; Hashimoto, N.; Toyoshima, Hideo; Kojima, Fumio; Shimizu, Akihiro

doi:10.1109/4.165330

Cited by 37 publications

(3 citation statements)

References 9 publications

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“…12 The conventional current sense amplifier. Sensing delay of the current and voltage sense amplifier [131]. Figure 5.…”

Section: List Of Figuresmentioning

confidence: 99%

“…Sensing circuitry of a 7 ns 140 mW CMOS SRAM with current sense amplifier. 119Figure 5.14 Simulated voltage gain[131].…”

mentioning

confidence: 99%

“…The sensing delay is insensitive to bit-line capacitance since no capacitor discharging is required to sense the cell data. Therefore, current sense amplifier has better performance than voltage sense amplifier in terms of smaller delay and less current consumption.A high-speed current sense amplifier coupled with a pre-output buffer is portrayed inFigure 5.13[131]. This design successfully tackles the gain reduction problem of the conventional voltage sense amplifier as it offers a large voltage gain for bit-line voltages close to V D D-The control signal Oeq is the equalization signal for both the bit-lines and data-lines, whereas EQ represents the equalization signal for the terminals 51 and 52.…”

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confidence: 99%

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CMOS VLSI subsystems for low-voltage low-power applications

Kong¹

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My journey of PhD candidature at NTU has been a worthwhile experience, which is both challenging and fulfilling. In fact, in every important passage of our lives, there are always bound to be some special individuals whose support and contribution are essential in determining our success or failure. In my endeavor of pursuing PhD, the first person to whom, I want to thank is none other than my dissertation advisor, Associate Professor Yeo Kiat Seng. I would like to express my deepest gratitude to him for his willingness and readiness to invest time into giving me adequate and timely guidance despite his very tight schedule. The numerous discussion and brainstorming sessions with him were intellectually inspiring and enlightening. The continuous support and confidence he bestowed upon me was invaluable in steering this dissertation to completion through all its phases. It is also my great pleasure to express my heartfelt appreciation to Associate Professor Chang Chip Hong for sharing his expertise with me and providing insightful comments on my research work. I would like to extend my special thanks to the technical staffs of the Centre for Integrated Circuits and Systems (CICS), Mr. Sia Liang Poo, Mr. Jimmy, and Mr. William for the countless help and assistance they have been offering me throughout my stay in the laboratory. Next, to my peers Gu Jiangmin, Phyu Myint Wai, Chia Leong Yap, Li Qiang, He Yajuan, and Liu Haiqi, thanks for your genuine acquaintance and I will never forget the many wondrous moments we have spent together. The beautiful moments will be forever fresh in mind. Last but not least, I would like to convey my heartfelt appreciation to my parents, siblings and my loved ones for steadfastly standing by me throughout the years, through thick and thin. Words can never express the warmth and thankfulness I feel for each one of them. I want to thank my dear husband, Kam Chew, for his enormous support and endless love, patience and encouragement. The unwavering trust and wholehearted support he has given me all this while will be eternally engraved into my memory. With this, I dedicate this doctorate to them.

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“…12 The conventional current sense amplifier. Sensing delay of the current and voltage sense amplifier [131]. Figure 5.…”

Section: List Of Figuresmentioning

confidence: 99%

“…Sensing circuitry of a 7 ns 140 mW CMOS SRAM with current sense amplifier. 119Figure 5.14 Simulated voltage gain[131].…”

mentioning

confidence: 99%

mentioning

confidence: 99%

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CMOS VLSI subsystems for low-voltage low-power applications

Kong¹

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Sram Chips

Carns¹,

Zheng²,

Wang³

1999

Wiley Encyclopedia of Electrical and Electronics Engineering

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The sections in this article are The Basics of Memory Operation The Fundamental Components of the Sram Cell Inverter Analysis and Comparison The Fundamental Components of the Basic Sram Architecture Improving Today'S Sram Cell Cost and Performance Application‐Specific Sramss Sram Testing and Reliability Novel Sram Cell Configurations for Future High‐Speed/High‐Density Applications

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Low-Power CMOS Random Access Memory Circuits

Bellaouar

Elmasry

1995

Low-Power Digital VLSI Design

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A 7-ns 140-mW 1-Mb CMOS SRAM with current sense amplifier

Cited by 37 publications

References 9 publications

CMOS VLSI subsystems for low-voltage low-power applications

CMOS VLSI subsystems for low-voltage low-power applications

Sram Chips

Low-Power CMOS Random Access Memory Circuits

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