A 75.1dB SNDR, 80.2dB DR, 4th-order feed-forward continuous-time sigma-delta modulator with hybrid integrator for silicon TV-tuner application

Ho, Chen-Yen; Lee, Zwei-Mei; Huang, Mu-Chen; Huang, Sheng-Jui

doi:10.1109/asscc.2011.6123560

Cited by 2 publications

(1 citation statement)

References 4 publications

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“…An alternative solution is to integrate the weighted addition into the last integrator [34]. This solution, however, imposes tougher requirements (e.g., larger output swing) on the last integrator.…”

Section: B Summation Quantizer and Feedback Dacmentioning

confidence: 99%

A Power-Efficient Continuous-Time Incremental Sigma-Delta ADC for Neural Recording Systems

Tao

Rusu

2015

IEEE Trans. Circuits Syst. I

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Abstract-This paper presents an analog-to-digital converter (ADC) dedicated to neural recording systems. By using two continuous-time incremental sigma-delta ADCs in a pipeline configuration, the proposed ADC can achieve high-resolution without sacrificing the conversion rate. This two-step architecture is also power-efficient, as the resolution requirement for the incremental sigma-delta ADC in each step is significantly relaxed. To further enhance the power efficiency, a class-AB output stage and a dynamic summing comparator are used to implement the sigma-delta modulators. A prototype chip, designed and fabricated in a standard 0.18 µm CMOS process, validates the proposed ADC architecture. Measurement results show that the ADC achieves a peak signal-to-noise-plus-distortion ratio of 75.9 dB over a 4 kHz bandwidth; the power consumption is 34.8 µW, which corresponds to a figure-of-merit of 0.85 pJ/conv.

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Section: B Summation Quantizer and Feedback Dacmentioning

confidence: 99%

A Power-Efficient Continuous-Time Incremental Sigma-Delta ADC for Neural Recording Systems

Tao

Rusu

2015

IEEE Trans. Circuits Syst. I

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A Systematic Method for Scaling Coefficients of the Continuous-Time Low-Pass ΣΔ Modulator Using a Simulink-Based Toolbox

Zaky,

Hosny,

Omran

et al. 2023

Eng

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The sigma-delta modulator (SDM) is one of the well-established data converter architectures. It is well-known for achieving a high signal-to-noise ratio (SNR). In the SDM, the integrators in the loop filter could suffer from overloading if the signal swing exceeds its maximum level, which leads to performance and SNR degradation. Thus, scaling the system coefficients is needed, such that there is no overloading for the integrators. In this work, we present a systematic general method that could be used for scaling the signal swings in the continuous-time low-pass sigma-delta modulator (SDM). The proposed method can be applied to any continuous-time low-pass SDM architecture, and it includes the scaling of all the possible combinations of the system coefficients. Moreover, an open-source Simulink-based toolbox that includes the systematic method is presented. This toolbox could help the designer to execute the scaling process and the simulations in an efficient way. In addition to that, a design example is discussed to illustrate the proposed method, wherein the presented toolbox is used for simulations, and the simulation results are shown.

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A 75.1dB SNDR, 80.2dB DR, 4th-order feed-forward continuous-time sigma-delta modulator with hybrid integrator for silicon TV-tuner application

Cited by 2 publications

References 4 publications

A Power-Efficient Continuous-Time Incremental Sigma-Delta ADC for Neural Recording Systems

A Power-Efficient Continuous-Time Incremental Sigma-Delta ADC for Neural Recording Systems

A Systematic Method for Scaling Coefficients of the Continuous-Time Low-Pass ΣΔ Modulator Using a Simulink-Based Toolbox

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