A 750V recessed-emitter-trench IGBT with recessed-dummy-trench structure featuring low switching losses

Yao, Yao; Luo, Hailin; Xiao, Qiang; Zhu, Cancan; Xiao, Haibo; Qin, Rongzhen; Ning, Xubin; Tan, C. S.; Deviny, Ian; Dai, Xiaoping

doi:10.1109/ispsd.2018.8393615

Cited by 9 publications

(5 citation statements)

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“…To break through the limitation of the N cs on the device performance, various improved methods were proposed, such as narrow mesa structure, buried p layer structure, shield emitter trench (SET), split gate (SG) and recessed emitter trench (RET) structure, etc. [8]- [14]. Acting as a dummy trench, the emitter-connected RET for the RET CSTBT reduces the mesa width without increasing the complexity of the contact process.…”

mentioning

confidence: 99%

Low Loss and Low EMI Noise CSTBT With Split Gate and Recessed Emitter Trench

Zhang

Xiao

Zhu

et al. 2021

IEEE J. Electron Devices Soc.

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A novel carrier stored trench bipolar transistor (CSTBT) with split gate (SG) and recessed emitter trench (SGRET CSTBT) is proposed. The proposed device features a SG structure with thicker oxide layer under the trench gate and recessed trench emitter, respectively. Compared with the conventional CSTBT with recessed emitter trench (RET CSTBT), the proposed device not only significantly reduces the gate-collector capacitance (C GC ) but also alleviates the negative impact of the heavily doped n-type carrier stored layer on the breakdown voltage (BV). Simulation results show that with the similar BV of about 650V, the on-state voltage drop (V ceon ) at J ce =200A/cm 2 for the proposed SGRET CSTBT is only 1.11V, which is 0.19V lower than that of the conventional RET CSTBT. Moreover, compared with the conventional RET CSTBT, the C GC at the V ce of 25V, total gate charge (Q G ) and miller plateau charge (Q GC ) for the proposed device are reduced by 84.3%, 38.6% and 51.6%, respectively. As a result, the trade-off relationship between the V ceon and turn-off loss (E off ) as well as trade-off relationship between the turn-on loss (E on ) and dV ak /dt of the free-wheeling diode (FWD) are significantly improved for the proposed device. At the same V ceon of 1.16V, the E off is reduced from 9.2mJ/cm 2 of the conventional one to 3.3mJ/cm 2 of the proposed device. At the same E on of 8.3mJ/cm 2 , the dV ak /dt of FWD for the proposed device is reduced by 24.5% compared with that of the conventional RET CSTBT, which significantly suppresses the EMI noise.INDEX TERMS CSTBT, split gate (SG), recessed emitter trench (RET), electromagnetic interference (EMI), turn-on loss (E on ), turn-off loss (E off ), on-state voltage drop (V ceon ), free-wheeling diode (FWD).

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mentioning

confidence: 99%

Low Loss and Low EMI Noise CSTBT With Split Gate and Recessed Emitter Trench

Zhang

Xiao

Zhu

et al. 2021

IEEE J. Electron Devices Soc.

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“…Proposed brief fabrication process flow of the DSS-CSTBT: (a) select the N-type FZ substrate, (b) etch emitter and gate trenches simultaneously, (c) form thick oxide layer, (d) etch the upper part of the oxide layer in the gate trench, (e) form gate oxide layer on the sidewall of the gate trench, (f) fill trench with poly-silicon, (g) form the N-CS layer, P body , N+ region, P+ region, and metal in surface, (h) form the backside structures. 1.5×10 17 1.5×10 17 CS layer doping (cm −3 ) 1.5-3.5×10 16 1.5×10 16 N-drift doping (cm −3 ) 7×10 13 7×10 13 FS layer doping (cm −3 ) 2×10 16 2×10 16 P + collector doping (cm −3 ) 2×10 17 2×10 17…”

Section: Device Structure and Mechanismmentioning

confidence: 99%

“…[8][9][10][11][12] Therefore, to further improve the device performance, many im-proved CSTBT structures, such as p-type buried layer (PBL) structure, alternated trench IGBT with PBL structure, recessed emitter trench (RET) structure and split gate (SG) structure, have been proposed. [13][14][15][16][17][18][19] Although device performance is significantly improved for these structures, the contradiction between V CEON and E OFF for the CSTBT is still prominent, which limits the further reduction of the device power loss and improvement of the power density.…”

Section: Introductionmentioning

confidence: 99%

High performance carrier stored trench bipolar transistor with dual shielding structure

et al. 2023

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A novel high performance carrier stored trench bipolar transistor (CSTBT) with dual shielding structure (DSS-CSTBT) is proposed in this paper. The proposed DSS-CSTBT features a double trench structure with different trench profiles in the surface, in which a shallow gate trench is shielded by a deep emitter trench and a thick oxide layer under it. Compared with the conventional CSTBT (Con-CSTBT), the proposed DSS-CSTBT not only alleviates the negative impact of the shallow gate trench and highly doped CS layer on the breakdown voltage (BV) but also well reduces the gate-collector capacitance (C GC), gate charge (Q G) and turn off loss (E OFF) of the device. Furthermore, lower turn on loss (E ON) and gate drive loss (E DR) are also obtained. Simulation results show that with the same CS layer doping concentration (N CS) of 1.5×1016 cm-3, the BV increases from 1312 V of the Con-CSTBT to 1423 V of the proposed DSS-CSTBT with oxide layer thickness under gate (T og2) of 1μm. Moreover, compared with the Con-CSTBT, the C GC at V CE of 25 V and miller plateau charge (Q GC) for the proposed DSS-CSTBT with T og2 of 1μm are reduced by 79.4% and 74.3%, respectively. With the V GE increases from 0 V to 15 V, the total Q G for the proposed DSS-CSTBT with T og2 of 1μm is reduced by 49.5%. As a result, at the same on-state voltage drop (V CEON) of 1.55 V, the E ON and E OFF are reduced from 20.3 mJ/cm2 and 19.3 mJ/cm2 for the Con-CSTBT to 8.2 mJ/cm2 and 9.7 mJ/cm2 for the proposed DSS-CSTBT with T og2 of 1μm, respectively. Thus, the proposed DSS-CSTBT not only significantly improves the trade-off relationship between the V CEON and E OFF but also greatly reduces the E ON.

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“…To purchase an overall optimisation in terms of static, dynamic, and short‐circuit characteristics, some combined technologies are proposed, such as the improved RET and Recessed Dummy Trench (RDT) structures shown in Fig. 22 [55].…”

Section: Technology Trend For More Reliable Power Semiconductors Ofmentioning

confidence: 99%

Recent advances and trend of HEV/EV‐oriented power semiconductors – an overview

Liu¹,

Wang

et al. 2020

IET Power Electronics

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This study introduces the development advances and trend of power semiconductors used in hybrid and electric vehicles (HEV/EV). The status and forecast of power electronics' requirement in HEV/EV are discussed along with a review of the automotive standard of power semiconductor devices. The advances in automotive semiconductor technologies such as Sibased insulated-gate bipolar transistor (IGBT) and freewheeling diode (FRD) and SiC-based metal oxide semiconductor fieldeffect transistor (MOSFET) and Schottky barrier diode are presented. The advances in automotive semiconductor packaging technologies are illustrated from three considerations, which are the low inductance in high-power density packaging, lower thermal resistance designing, and advanced packaging technologies. The challenges and development trend of more reliable power semiconductors for HEV/EV are discussed. The challenges in Si devices are focused on power density, efficiency, reliability, and packages, while the high temperature and low inductances are the main challenges for SiC devices. Lastly, the development trend is discussed in terms of four aspects, the new generation Si IGBT for HEV/EV, such as recessed-emittertrench, reverse-conduction-IGBT, and smart IGBT; next generation SiC MOSFET; new packaging technology and material, such as planar packaging.

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A 750V recessed-emitter-trench IGBT with recessed-dummy-trench structure featuring low switching losses

Cited by 9 publications

References 1 publication

Low Loss and Low EMI Noise CSTBT With Split Gate and Recessed Emitter Trench

Low Loss and Low EMI Noise CSTBT With Split Gate and Recessed Emitter Trench

High performance carrier stored trench bipolar transistor with dual shielding structure

Recent advances and trend of HEV/EV‐oriented power semiconductors – an overview

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